Q:你说的是GGMOS或者GCMOS?
A: for IO, i do not recommend you to use gate coupled MOS as ESD protection.
Q: 你说的是GGMOS或者GCMOS?
A: if you want to reduce the parasitic capacitance, use pure diode.
Q: V1,V3不用,可以么?
A: yes, if you don't care about V1 and V3, and the chip will function well even if V1 and V3 are damaged by ESD stress.
也不一定要加电阻。什么工艺,我没用过工艺提供的PDIO和NDIO二极管。自己画的,1.5um*20um, 3 finger is enough for 0.18um CMOS process. if you want to add resisitor, 100~200ohm is usually used.
我想PDIO应该是P+/Nwell diode, NDIO是N+/Pwell diode
for IO to GND, use N+/Pwell diode
for IO to VDD, use P+/Nwell diode.
or you can use P+/Nwell diode for both.