Synopsys donation to the IEEE P1450.6.2 Working Group:
Standard for Memory Modeling in Core Test Language (CTL)
TetraMax uses a limited Verilog behavioral syntax to define RAM and ROM models for ATPG. This is equivalent to defining simple RAM/ROM functional models. This document provides description of TetraMax memory modeling concepts using examples.
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发表于 2010-6-25 13:05:20
发表于 2010-7-2 08:31:06
