如何写约束

fourrivers

楼主说的是input delay和output delay？按60％给吧

yinchyang

The value of input delay and output delay can not always be 60%, they should be defined according to
logic path to or from the ports,
If the logic is be registered before it was sent to output port, the output delay can be set near to the clock period.
The same reason for input port, if the signal is registered first from ports, the input delay can be set near to clock period.
If the logic path is complex, you should assume the value .

fourrivers

说得对，关键是楼主的问题太模糊。我只是给他一个经验值。
要想写好约束，当然要具体问题具体分析了。