for power analysis, I think you need special tool such as PrimeTime to do it.
the files needed as follows:
1.design verilog netlist ,sdc ,parasitic files like SPEF file extracted by StarRC
2.synopsys timing library .db files
3.post simulation VCD files or saif files,during the post simulation, you may add the dumvar command in the testbench code
the power cosumption is related to the testbench that you give,which define the toggle rate of each net.
Hope this can help you. |