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楼主 |
发表于 2010-4-21 09:40:54
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你原来的模块就是这样的思路?没有高倍率采样你怎么采得到正确的信号?你写的和UART的要求的差距很大
falloutmx 发表于 2010-4-20 17:14
原来这个模块是这样的,我用这个模块试了一下没问题,从仿真来看,感觉区别就是它的输出比改了以后的模块提前了半个多周期
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:53:51 04/15/2010
// Design Name:
// Module Name: rev
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module rev(
rst,
clk50,
rxd,
odata,
received_char
);
input rst;
input clk50;
input rxd;
output [7:0]odata;
output received_char;
reg rxd_reg;
reg [7:0]rev_char;
reg rev_check;
reg [2:0] REV_state;
reg [3:0] rev_bits_count;
reg [13:0] REV_counter;
reg received_char;
parameter DELAYCOUNT= 14'b01_0100_0101_0110; //5206+1+1=5208
parameter BITS_PER_CHAR=3'b110; //6+1+1=8
parameter REV_IDLE=3'b000,
REV_START=3'b001,
REV_BIT=3'b010,
REV_CHECK=3'b101,
REV_STOP=3'b100;
assign odata=rev_char;
always @ (posedge clk50)
begin
if(~rst)
begin
rxd_reg<=1;
end
else
begin
rxd_reg<=rxd;
end
end
//state machine
always @ (posedge clk50)
if(~rst)
begin
rev_char<=8'b0;
REV_counter<=DELAYCOUNT;
REV_state<=REV_IDLE;
rev_bits_count<=BITS_PER_CHAR;
received_char<=0;
end
else
case(REV_state)
REV_IDLE: begin
REV_counter<=DELAYCOUNT;
rev_bits_count<=BITS_PER_CHAR;
received_char<=0;
rev_check<=0;
rev_char<=8'b0;
if(~rxd_reg)
begin
REV_state<=REV_START;
end
end
REV_START: begin
if(REV_counter[13])
begin
REV_state<=REV_BIT;
REV_counter<=DELAYCOUNT;
end
else
REV_counter<=REV_counter-1;
end
REV_BIT: begin
if(REV_counter[13])
begin
REV_state<=REV_BIT;
REV_counter<=DELAYCOUNT;
if(rev_bits_count[3])
begin
REV_state<=REV_CHECK;
REV_counter<=DELAYCOUNT;
end
else
rev_bits_count<=rev_bits_count-1;
end
else
REV_counter<=REV_counter-1;
if(REV_counter==2500)
begin
rev_char[7:0]<={rxd_reg,rev_char[7:1]};
end
end
REV_CHECK: begin
if(REV_counter[13])
begin
REV_state<=REV_STOP;
REV_counter<=DELAYCOUNT;
received_char<=1;
end
else
REV_counter<=REV_counter-1;
if(REV_counter==2500)
begin
rev_check<=rxd_reg;
end
end
REV_STOP: begin
received_char<=0;
if(REV_counter[13])
begin
REV_state<=REV_IDLE;
REV_counter<=DELAYCOUNT;
end
else
REV_counter<=REV_counter-1;
end
default:
REV_state<=REV_IDLE;
endcase
endmodule |
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