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论文题名如下:
1 A 1-V +31 dBm IIP3, Reconfigurable, Continuously Tunable, Power-Adjustable Active-RC LPF
2 A 3.1 GHz–8.0 GHz Single-Chip Transceiver for MB-OFDM UWB in 0.18-$mu$ m CMOS Process
3 A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS
4 A 750 Mb per s, 12 pJ per b, 6-to-10 GHz CMOS IR-UWB Transmitter With Embedded On-Chip Antenna
5 A Fully Integrated 7.3 kV HBM ESD-Protected Transformer-Based 4.5–6 GHz CMOS LNA
6 A Low-Power, Linearized, Ultra-Wideband LNA Design Technique
7 A Rail-To-Rail Class-AB Amplifier With an Offset Cancellation for LCD Drivers
8 A RF to DC Voltage Conversion Model for Multi-Stage Rectifiers in UHF RFID Transponders
9 A Single-Chip Ultra-Wideband Receiver With Silicon Integrated Antennas for Inter-Chip Wireless Interconnection
10 A Single-Inductor Step-Up DC-DC Switching Converter With Bipolar Outputs for Active Matrix OLED Mobile Display Panels
11 A Slew Controlled LVDS Output Driver Circuit in 0.18 $mu$m CMOS Technology
12 A Wideband Power Detection System Optimized for the UWB Spectrum
13 An Energy Efficient 40 Kb SRAM Module With Extended Read-Write Noise Margin in 0.13 $mu$m CMOS
14 An Improved Active Decoupling Capacitor for “Hot-Spot” Supply Noise Reduction in ASIC Designs
15 Analysis and Design of an Integrated Notch Filter for the Rejection of Interference in UWB Systems
16 Analysis of the Influence of Substrate on the Performance of On-Chip MOS Decoupling Capacitors
17 Combined Linear and $Delta$-Modulated Switch-Mode PA Supply Modulator for Polar Transmitters
18 Design and Analysis of Actively-Deskewed Resonant Clock Networks
19 Design and Measurement of a CT $DeltaSigma$ ADC With Switched-Capacitor Switched-Resistor Feedback
20 Energy–Delay Optimization of 64-Bit Carry-Lookahead Adders With a 240 ps 90 nm CMOS Design Example
21 Fast Low Power eDRAM Hierarchical Differential Sense Amplifier
22 HDTV1080p H.264-AVC Encoder Chip Design and Performance Analysis
23 High-Speed Single-Ended Parallel Link Based on Three-Level Differential Encoding
24 LC PLL With 1.2-Octave Locking Range Based on Mutual-Inductance Switching in 45-nm SOI CMOS
25 Low Voltage, Low Power, Inverter-Based Switched-Capacitor Delta-Sigma Modulator
26 Method for a Constant Loop Bandwidth in LC-VCO PLL Frequency Synthesizers
27 Robust SRAM Design via BIST-Assisted Timing-Tracking (BATT)
28 SRAM Cell Stability-A Dynamic Perspective
29 Systematic Transistor and Inductor Modeling for Millimeter-Wave Design |
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JSSC_2009_Issue_2.part01.rar
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JSSC_2009_Issue_2.part02.rar
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JSSC_2009_Issue_2.part03.rar
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JSSC_2009_Issue_2.part04.rar
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JSSC_2009_Issue_2.part05.rar
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JSSC_2009_Issue_2.part06.rar
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JSSC_2009_Issue_2.part07.rar
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JSSC_2009_Issue_2.part08.rar
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JSSC_2009_Issue_2.part09.rar
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