西安万思微电子公司招聘信息

szhtianli

ASIC逻辑设计工程师Logic Design Engineer or trainee（数名）

Job Function职责描述：
A)Design digital circuit blocks using RTL coding in mixed signal IC chips.使用RTL代码设计数字逻辑电路（用于混合信号IC）
B)Write RTL code for custom designed blocks such as SRAM and adder blocks.编写客户定制RTL代码，例：SRAM，加法器等
C)Define micro architecture of digital part of the mixed signal IC.定义混合信号IC数字部分微架构
D)Verification of the logic blocks using test bench and Vera.使用test bech和VERA语言验证逻辑功能块
E)Use FPGA to validate the designed blocks. 使用FPGA验证设计模块
F)Write synthesis script to generate gate level netlist.编写综合教本产生门级网表
G)Analyze timing for synthesized blocks.分析综合模块时序

Candidates must have the following qualifications: 任职要求：
A)1 years RTL coding experience.1年RTL代码经验
B)Understanding of concept of state-machine.了解状态机概念
C)Understanding of the concept of timing. Able to perform static timing analysis.具备时序概念，能进行静态时序分析
D)Familiar with VCS or NC-Verilog熟悉VCS 或 Verilog
E)Able to write and use test-bench to test RTL blocks.可以编写和使用测试平台测试RTL模块
F)Able to program FPGA to test logic blocks.可以使用FPGA编程测试逻辑模块


欢迎您的加盟！公司地址：西安高新一路25号创新大厦N708 Email：amtsemi_hr@126.com 联系电话：029-88312307 联系人：Mr Jiao

szhtianli

欢迎您的加盟！
公司地址：西安高新一路25号创新大厦N708
Email：amtsemi_hr@126.com
联系电话：029-88312307
联系人：Mr Jiao

小小xxl

hai hao

yingzi1930

楼主招不招版图啊