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Data Transmission Theory数据传输理论[经典数字通信讲义]Stanford教授，IEEE会士 John M. Cioffi
6 Fundamentals of Synchronization 497 6.1 Phase computation and regeneration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498 6.1.1 Phase Error Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498 6.1.2 Voltage Controlled Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501 6.1.3 Maximum-Likelihood Phase Estimation . . . . . . . . . . . . . . . . . . . . . . . . 503 6.2 Analysis of Phase Locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503 6.2.1 Continuous Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503 6.2.2 Discrete Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505 6.2.3 Phase-locking at rational multiples of the provided frequency . . . . . . . . . . . . 509 6.3 Symbol Timing Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509 6.3.1 Open-Loop Timing Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509 6.3.2 Decision-Directed Timing Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . 512 6.3.3 Pilot Timing Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514 6.4 Carrier Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514 6.4.1 Open-Loop Carrier Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514 6.4.2 Decision-Directed Carrier Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . 515 6.4.3 Pilot Carrier Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516 6.5 Frame Synchronization in Data Transmission . . . . . . . . . . . . . . . . . . . . . . . . . 516 6.6 Pointers and Add/DeleteMethods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516 Exercises - Chapter 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517 Fundamentals of Synchronization The analysis and developments of Chapters 1-4 presumed that the modulator and demodulator are synchronized. That is, both modulator and demodulator know the exact symbol rate and the exact symbol phase, and where appropriate, both also know the exact carrier frequency and phase. In practice, the common (receiver/transmitter) knowledge of the same timing and carrier clocks rarely occurs unless some means is provided for the receiver to synchronize with the transmitter. Such synchronization is often called phase-locking. In general, phase locking uses three component operations as generically depicted in Figure 6.1:1 1. Phase-error generation - this operation, sometimes also called .phase detection,. derives a phase difference between the received signal.s phase θ(t) and the receiver estimate of this phase, .θ(t). The actual signals are s(t) = cos (ωlot + θ(t)) and .s(t) = cos phase difference is of interest in synchronization. This difference is often called the phase error, φ(t) = θ(t) − .θ(t). Various methods of phase-error generation are discussed in Section 6.1. 2. Phase-error processing - this operation, sometimes also called .loop Þltering. extracts the essential phase difference trends from the phase error by averaging. Phase-error processing typically rejects random noise and other undesirable components of the phase error signal. Any gain in the phase detector is assumed to be absorbed into the loop Þlter. Both analog and digital phase-error processing and the general operation of what is known as a .phase-lock loop,. are discussed in 3. Local phase reconstruction - this operation, which in some implementations is known as a .voltage-controlled oscillator. (VCO), regenerates the local phase from the processed phase error in an attempt to match the incoming phase, θ(t). That is, the phase reconstruction tries to force φ(t) = 0 by generation of a local phase .θ(t) so that .s(t) matches s(t). Various types of voltage controlled oscillators and other methods of regenerating local clock are also discussed in Section Any phase-locking mechanism will have some Þnite delay in practice so that the regenerated local phase will try to project the incoming phase and then measure how well that projection did in the form of a new phase error. The more quickly the phase-lock mechanism tracks phase deviations in phase, the more susceptible it will be to random noise and other imperfections. Thus, the communication engineer must trade these two competing effects appropriately when designing a synchronization system. The design of the transmitted signals can facilitate or complicate this trade-off. These design trade-offs will be generally examined in Section 6.2. In practice, unless pilot or control signals are embedded in the transmitted signal, it is necessary either to generate an estimate of transmitted signal.s clocks or to generate an estimate of the phase error directly. Sections 6.3 and 6.4 speciÞcally examine phase detectors for situations where such clock extraction is necessary for timing recovery (recovery of the symbol clock) and carrier recovery (recovery of the phase of the carrier in passband transmission), respectively. In 1These operations may implemented in a wide variety of ways. Figure 6.1: General phase-lock loop structure. addition to symbol timing, data is often packetized or framed. Methods for recovering frame boundary are discussed in Section 6.5. Pointers and add/delete (bit robbing/stuffing) are speciÞc mechanisms of local phase reconstruction that allow the use of asynchronous clocks in the transmitter and receiver. These methods Þnd increasing use in modern VLSI implementations of receivers and are discussed in 6.1 Phase computation and regeneration This section describes the basic operation of the phase detector and of the voltage-controlled oscillator (VCO) in Figure 6.1 in more detail. 6.1.1 Phase Error Generation Phase-error generation can be implemented continuously or at speciÞc sampling instants. The discussion in this subsection will therefore not use a time argument or sampling index on phase signals. That is Ideally, the two phase angles, θ, the phase of the input sinusoid s, and .θ, the estimated phase produced at the VCO output, would be available. Then, their difference φ could be computed directly. DeÞnition 6.1.1 (ideal phase detector) A device that can compute exactly the difference φ = θ − .θ is called an ideal phase detector. Ideally, the receiver would have access to the sinusoids s = cos(θlo + θ) and .s = cos(θlo + .θ) where θlo is the common phase reference that depends on the local oscillator frequency; . θlo is consequence to the ensuing arguments. A seemingly straightforward method to compute the phase error would then be to compute θ, the phase of the input sinusoid s, and .θ, the estimated phase, according to θ = ±arccos [s] − θlo ; .θ = ±arccos [.s] − θlo . (6.1) Then, φ = θ − .θ, to which the value θlo is inconsequential. However, a reasonable implementation of the arccos function can only produce angles between 0 and π, so that φ would then always lie between Figure 6.3: Demodulating phase detector. −π and π. Any difference of magnitude greater than π would be thus effectively be computed modulo (−π, π). The arccos function could then be implemented with a look-up table. DeÞnition 6.1.2 (mod-2π phase detector) The arccos look-up table implementation of the phase detector is called a modulo-2π phase detector2. The characteristics of the mod-2π phase detector and the ideal phase detector are compared in Figure 6.2. If the phase difference does exceed π in magnitude, the large difference will not be exhibited in the phase error φ - this phenomenon is known as a .cycle slip,. meaning that the phase lock loop missed (or added) an entire period (or periods) of the input sinusoid. This is an undesirable phenomena in most applications, so after a phase-lock loop with mod-2π phase detector has converged, one tries to ensure that |φ| cannot exceed π. In practice, a good phase lock loop should keep this phase error as close to zero as possible, so the condition of small phase error necessary for use of the mod-2π phase detector is DeÞnition 6.1.3 (demodulating phase detector) Another commonly encountered phase detector, both in analog and digital form, is the demodulating phase detector shown in −sin(θlo + .θ) · cos(θlo + θ) 2Sometimes also called a .sawtooth. phase detector after the phase characteristic in Figure 6.2. Figure 6.4: Sampling phase detector. and . f is a lowpass Þlter that is cascaded with the phase-error processing in the phase-locking The basic concept arises from the relation −where the sum-phase term (Þrst term on the right) can be eliminated by lowpass Þltering; this lowpass Þltering can be absorbed into the loop Þlter that follows the phase detector. The phase detector output is thus proportional to sin (φ). The usual assumption with this type of phase detector is that φ is small When φ is small, generation of the phase error thus does not require the arcsin function. Another way of generating the phase error signal is to use the local sinusoid to sample the incoming sinusoid as shown in Figure 6.4. If the rising edge of the local sinusoid is used for the sampling instant, (At this phase, .s = 0.) Then, at the time of this rising edge, the sampled sinusoid s has phase so that s(t) at these times tk is Such a phase detector is called a sampling phase detector. The lowpass Þlter .holds. the sample Another type of phase detector is the binary phase detector shown in Figure 6.5. In the binary phase detector, the phase difference between the two sinusoids is approximately the width of the high signals at point C in Figure 6.5. The hard limiters are used to covert the sinusoids into 1/0 square waves or binary signals. The adder is a binary adder. The lowpass Þlter just averages (integrates) the error signal, so that its output is proportional to the magnitude of the phase error. The important sign of the phase error is determined by .latching. the polarity of .s when s goes high (leading-edge triggered 3When A and B are phase aligned, then φ = 0, so that the race condition that exists in the clocking and data set-up on line B should not be of practical signiÞcance if sufficiently high-speed logic is used. Figure 6.5: Binary phase detector. 6.1.2 Voltage Controlled Oscillators The voltage controlled oscillator basically generates a sinusoid with phase difference (or derivative) proportional to the input control voltage e(t). DeÞnition 6.1.4 (Voltage Controlled Oscillator) An ideal voltage controlled oscil- lator (VCO) has an output sinusoid with phase .θ(t) that is determined by an input error or control signal according to in continuous time, or approximated by .θk+1 = .θk + kvco · ek . (6.9) Analog VCO physics are beyond the scope of this text, so it will suffice to just state that devices satisfying (6.8) are readily available in a variety of frequency ranges. When the input signal ek in discrete time is digital, the VCO can also be implemented with a look-up table and adder according to (6.9) whose output is used to generate a continuous time sinusoidal equivalent with a DAC. This implementation is often called a numerically controlled oscillator or NCO. Yet another implementation that can be implemented in digital logic on an integrated circuit is shown in Figure 6.6. The high-rate clock is divided by the value of the control signal (derived from ek) by connecting the true output of the comparator to the clear input of a counter. The higher the clock rate with respect to the rates of interest, the Þner the resolution on specifying .θk. If the clock rate is 1/T 0, then the divider value is p or p+1, depending upon whether the desired clock phase is late or early, respectively. A maximum phase change with respect to a desired phase (without external smoothing) can thus be T0/2. For 1% clock accuracy, then the master clock would need to be 50 times the generated Figure 6.6: Discrete-time VCO with all-digital realization. clock frequency. With an external analog smoothing of the clock signal (via bandpass Þlter centered around the nominal clock frequency), a lower frequency master clock can be used. The Voltage-Controlled Crystal Oscillator (VCXO) In many situations, the approximate clock frequency to be derived is known accurately. Conventional crystal oscillators usually have accuracies of 50 parts per million (ppm) or better. Thus, the VCO need only track over a small frequency/phase range. Additionally in practice, the derived clock may be used to sample a signal with an Analog-to-Digital converter. Such an ADC clock should not jitter about its nominal value (or signiÞcant signal distortion can be incurred). In this case, a VCXO normally replaces the VCO. The VCXO employs a crystal (X) of nominal frequency to stabilize the VCO close to the nominal value. Abrupt changes in phase are not possible because of the presence of the crystal. However, the high stability and slow variation of the clock can be of crucial importance in digital receiver designs. Thus, VCXO.s are used instead of VCO.s in designs where high stability sample clocking is The effect of oscillator jitter is approximated for a waveform x(t) according to A signal-to-jitter-noise ratio can be deÞned by For the highest frequency component of x(t) with frequency fmax, the SNR becomes which illustrates a basic time/frequency uncertainty principle: If (δt)2 represents jitter in squared sec- onds, then jitter must become smaller as the spectrum of the signal increases. An SNR of 20 dB (factor of 100) with a signal with maximum frequency of 1 MHz would suggest that jitter be below 16 ns. s(t) [ t (t)] lo = cosù +è s(t ) [ t (t)] lo ˆ = cosù +èˆ ö (t) =è (t)−èˆ(t) (t) k e(t)dt vco ∫ ⋅ = èˆ Figure 6.7: Continuous-time PLL with loop Þlter. 6.1.3 Maximum-Likelihood Phase Estimation A number of detailed developments on phase lock loops attempt to estimate phase from a likelihood Maximization of such a function can be complicated mathematically, often leading to a series of ap- proximations for various trigonometric functions that ultimately lead to a quantity proportional to the phase error that is then used in a phase-lock loop. Such approaches are acknowledged here, but those interested in the ultimate limits of synchronization performance are referred elsewhere. 6.2 Analysis of Phase Locking Both continuous-time and discrete-time PLL.s are analyzed in this section. In both cases, the loop- Þlter characteristic is speciÞed for both Þrst-order and second-order PLL.s. First-order loops are found to track only constant phase offsets, while second-order loops can track both phase and/or frequency The continuous-time PLL has a phase estimate that follows the differential equation θ(t) = kvco · f(t) ∗ The transfer function between PLL output phase and input phase is with s the Laplace transform variable. The corresponding transfer function between phase error and The cases of both Þrst- and second-order PLL.s are shown in Figure 6.7 with β = 0 reducing the diagram to a Þrst-order loop. The Þrst order PLL has a constant so that phase errors are simply integrated by the VCO in an attempt to set the phase .θ such that φ = 0. When φ =0, there is zero input to the VCO and the VCO output is a sinusoid at frequency ωlo. Convergence to zero phase error only happens when s(t) and .s(t) have the same frequency (ωlo) with initially a constant phase difference that can be driven to zero under the operation of the Þrst-order The response of the Þrst-order PLL to an initial phase offset (θ0) with .θ(t) = θ0 − θ0 · e−αt · u(t) (6.21) where u(t) is the unit step function (=1, for t > 0, = 0 for t < 0). For stability, α > 0. Clearly An easier analysis of the PLL Þnal value is through the Þnal value theorem: so that the Þnal phase error is zero for a unit-step phase input. For a linearly varying phase (that is a constant frequency offset), θ(t) = (θ0 + Δt)u(t), or where Δ is the frequency offset In this case, the Þnal value theorem illustrates the Þrst-order PLL.s eventual phase error is A larger .loop gain. α causes a smaller the offset, but a Þrst-order PLL cannot drive the phase error to zero. The steady-state phase instead lags the correct phase by Δ/α. However, larger α forces larger the bandwidth of the PLL. Any small noise in the phase error then will pass through the loop with less attenuation by the PLL, leading to a more noisy phase estimate. As long as |Δ/α| < π, then the modulo-2π phase detector functions with constant non-zero phase error. The range of Δ for which the phase error does not exceed π is known as the pull range of the PLL pull range = Δ < απ . (6.29) That is, any frequency deviation less than the pull range will result in a constant phase .lag. error. A better method by which to track frequency offset is the second-order PLL. The second order PLL uses the loop Þlter to integrate the incoming phase errors as well as pass the errors to the VCO. The integration of errors eventually supplies a constant signal to the VCO, which in turn forces the VCO output phase to vary linearly with time. That is, the frequency of the VCO can then be shifted away from ωlo permanently, unlike the operation with Þrst-order PLL. One easily veriÞes with the Þnal value theorem that for either constant phase or frequency offset (or for the second-order PLL. For stability, This subsection examines discrete-time Þrst-order and second-order phase-lock loops. Figure 6.8 is the discrete-time equivalent of Figure 6.1. Again, the Þrst-order PLL only recovers phase and not frequency. The second-order PLL recovers both phase and frequency. The discrete-time VCO follows .θk+1 = .θk + kvco · fk ∗ φk , (6.36) as the local phase at sampling time k. This expression assumes discrete .jerks. in the phase of the VCO. In practice, such transitions will be smoothed by any VCO that produces a sinusoidal output and the analysis here is only approximate for kT ≤ t ≤ (k + 1)T, where T is the sampling period. Taking the D-Transforms of both sides of (6.36) equates to D−1 · .Θ(D) = [1 − kvco · F(D)] · .Θ(D) + kvco · F(D) · Θ(D) . (6.37) The transfer function from input phase to output phase is 1 − (1 − kvco · F(D))D The transfer function between the error signal Φ(D) and the input phase is thus 1 − (1 − kvco · F(D))D D(1 − kvco · F(D)) − 1 F(D) determines whether the PLL is Þrst- or second-order. k [ lo k ] s = cosù kT +è [ ]k lo k sˆ = cosù kT +èˆ k k k ö =è −èˆ k k vco k k è =è + k ⋅ f ∗ö + Figure 6.8: Discrete-time PLL. First-Order Phase Lock Loop In the Þrst-order PLL, the loop Þlter is a (frequency-independent) gain α, so that For stability, |1 − α| < 1, or for stability. The closer α to 2, the wider the bandwidth of the overall Þlter from Θ(D) to .Θ(D), and the more (any) noise in the input sinusoid can distort the estimated phase. The Þrst-order loop can track and drive to zero any phase difference between a constant θk and .θk. To see this effect, the input phase θk = θ0 ∀ k ≥ 0 , (6.43) The phase error sequence then has transform D(1 − kvcoF(D)) − 1 (1 − D)(D(1 − α) − 1) and φ∞ → 0 if (6.42) is satisÞed. This result can also be obtained by the Þnal value theorem for one-sided D→1 (1 − D) · Φ(D) = 0 . (6.49) The Þrst-order loop will exhibit a constant phase offset, at best, for any frequency deviation between θk and .θk. To see this constant-lag effect, the input phase can be set to θk = Δ · k ∀ k ≥ 0 , (6.50) where Δ = ωoffsetT, which has D-Transform4 The phase-error sequence then has transform D(1 − kvco · F(D)) − 1 D(1 − kvco · F(D)) − 1 · (1 − D)(1 − D(1 − α)) This steady-state phase error can also be computed by the Þnal value theorem This constant-lag phase error is analogous to the same effect in the continuous-time PLL. Equation (6.55) can be interpreted in several ways. The main result is that the Þrst order loop cannot track a nonzero frequency offset Δ = ωoffsetT, in that the phase error cannot be driven to zero. For very small frequency offsets, say a few parts per million of the sampling frequency or less, the Þrst-order loop will incur only a very small penalty in terms of residual phase error (for reasonable α satisfying (6.42)). In this case, the Þrst-order loop may be sufficient in terms of magnitude of phase error, in tracking the frequency offset. In order to stay within the linear range of the modulo-2π phase detector (thereby avoiding cycle slips) after the loop has converged, the magnitude of the frequency offset |ωoffset| must T . The reader is cautioned not to misinterpret this result by inserting the maximum α (=2) into this result and concluding than any frequency offset can be tracked with a Þrst-order loop as long as the sampling rate is sufficiently high. Increasing the sampling rate 1/T at Þxed α, or equivalently increasing α at Þxed sampling rate, increase the bandwidth of the phase-lock loop Þlter. Any noise on the incoming phase will be thus less Þltered or .less rejected. by the loop, resulting in a lower quality estimate of the phase. A better solution is to often increase the order of the loop Þlter, resulting in the following second-order phase lock loop. As an example, let us consider a PLL attempting to track a 1 MHz clock with a local oscillator clock that may deviate by as much as 100 ppm, or equivalently 100 Hz in frequency. The designer may determine that a phase error of pi/20 is sufficient for good performance of the receiver. Then, α ≥ 40 · foffset ·T . (6.57) 4Using the relation that (D) dF dD ↔ kxk, with xk = Δ ∀ k ≥ 0. Then, since foffset = 100 Hz, and if the loop samples at the clock speed of 1/T = 106 MHz, then α > 4 × 10−3 . (6.58) Such a small value of α is within the stability bound of 0 < α < 2. If the phase error or phase estimate are relatively free of any .noise,. then this value is probably acceptable. However, if either the accuracy of the clock is less or the sampling rate is less, then an unacceptably large value of α can occur. Noise Analysis of the First-Order PLL If the phase input to the PLL (that is θk) has some zero-mean .noise. component σ2 θ , then the component of the phase error caused by the noise is 1 − [1 − α] · D · Nθ(D) (6.59) φk = (1 − α) · φk−1 + nθ,k − nθ,k−1 . (6.60) By squaring the above equation and Þnding the steady-state constant value σ2 Larger values of α create larger response to the input phase noise. If α → 2, the phase error variance becomes inÞnite. Small values of α are thus attractive, limiting the ability to keep the constant phase error small. The solution is to use the second-order PLL of the next subsection. Second-Order Phase Lock Loop In the second-order PLL, the loop Þlter is an accumulator of phase errors, so that This equation is perhaps better understood by rewriting it in terms of the second order difference equations for the phase estimate k = .Δk−1 + βφk (6.63) .θk+1 = .θk + αφk + .Δk (6.64) In other words, the PLL accumulates phase errors into a frequency offset (times T) estimate .Δk, which is then added to the Þrst-order phase update at each iteration. Then 1 − (2 − α − β)D + (1 − α)D2 , (6.65) . For stability, α and β must satisfy, 2 − 1.5α + 1 . (6.67) for real roots, which makes β << α since α + β < 1 in most designs. The second-order loop will track for any frequency deviation between θk and .θk. To see this effect, the input phase is again set to θk = Δk ∀ k ≥ 0 , (6.68) The phase error sequence then has transform D(1 − kvco · F(D) − 1) 1 − (2 − α − β)D + (1 − α)D2 · 1 − (2 − α − β)D + (1 − α)D2 (6.72) This steady-state phase error can also be by the Þnal value theorem D→1 (1 − D)Φ(D) = 0 . (6.73) Thus, as long as the designer chooses α and β within the stability limits, a second-order loop should be able to track any constant phase or frequency offset. One, however, must be careful in choosing α and β to reject noise, equivalently making the second-order loop too sharp or narrow in bandwidth, can also make its initial convergence to steady-state very slow. The trade-offs are left to the designer for any Noise Analysis of the Second-Order PLL This section to be added. Phase-Jitter Noise This section to be added. 6.2.3 Phase-locking at rational multiples of the provided frequency This section to be added. Sampling too slow. 6.3 Symbol Timing Synchronization Generally in data transmission, a sinusoid synchronized to the symbol rate is not supplied to the receiver. The receiver derives this sinusoid from the received data. Thus, the unabetted PLL.s studied so far would not be sufficient for recovering the symbol rate. The recovery of this symbol-rate sinusoid from the received channel signal, in combination with the PLL, is called timing recovery. There are two types of timing recovery. The Þrst type is called open loop timing recovery and does not use the receiver.s decisions. The second type is called decision-directed or decision-aided and uses the receiver.s decisions. Since the recovered symbol rate is used to sample the incoming waveform in most systems, care must be exerted in the higher-performance decision-directed methods that not too much delay appear between the sampling device and the decision device. Such delay can seriously degrade the performance of the receiver or even render the phase-lock loop unstable. Subsection 6.3.1 begins with the simpler open-loop methods and Subsection 6.3.2 then progresses to decision-directed methods. 6.3.1 Open-Loop Timing Recovery Probably the simplest and most widely used timing recovery method is the square-law timing recov- ery method of Figure 6.9. The present analysis ignores the optional preÞlter momentarily, in which case the nonlinear squaring device produces at its output Figure 6.9: Square-law timing recovery. The expected value of the square output (assuming, as usual, that the successively transmitted data symbols xm are independent of one another) is | 
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