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发表于 2010-7-29 09:05:07
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500MS/s 4-b Time Interleaved SAR ADC using Novel DAC Architecture
Sanjay G. Talekar, S. Ramasamy, G. Lakshminarayanan, B. Venkataramani
Dept. of ECE, National Institute of Technology, Tiruchirappalli
E-mail: laksh@nitt.edu, bvenki@nitt.edu |
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