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发表于 2014-7-24 14:37:00
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Technology
The A/D contains an internal DAC, SAR logic and a Comparator. Analog switches are
sequenced by successive approximation logic to match the analog difference input voltage
[VINP - VINN] to a corresponding digital value, the most significant bit is tested first. After 16
clocks’ period (including sampling, bit cycling, etc.), a digital 12-bit binary code (1111 1111 1111
= full-scale) is transferred to an output latch, and then an interrupt is asserted (INTRB makes a
high-to-low transition). A conversion in process can be interrupted by issuing a second start
command. The device may be operated in the free-running mode by connecting INTRB to the
WRB input with SLEEP=0. To ensure start-up under all possible conditions, an external WRB
pulse is required during the first power-up cycle.
On the high-to-low transition of the WRB input, the internal SAR latches and the shift register
stages are reset. As long as the SLEEP input and WRB input remain low, the A/D will remain
in reset state. Conversion will start after WRB input makes a low-to-high transition.
A functional block diagram of the A/D converter is shown in Fig. 9.
The converter is started by setting CS and WR to low concurrently, which sets the start flip-flop
(FF). The resulting “1” level resets the 12-bit shift register as well as the Interrupt (INTR) FF,
and inputs a “1” to the D flop-FF1, which is at the input end of the 12-bit shift register. Internal
clock signals then transfer this “1” to the Q output of FF1. The AND gate, G1, combines this “1”
output with a clock signal to provide a reset signal to the start FF. If the set signal is no longer
present (either WR or CS is at “1” level), the start FF is reset and the 12-bit shift register then
can have the “1” clocked in, which starts the conversion process. If the set signal was still
present, this reset pulse would have no effect (both outputs of the start FF would momentarily
be at “1” level) and the 12-bit shift register would keep on being held in the reset mode. This
logic therefore allows for wide CS and WR signals and the converter will start after at least one
of these signals reverts to high and the internal clocks again provide a reset signal for the start |
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