Digital Verification Engineer QUALIFICATION: Education:
Master degree from first rate engineering schools. Experience:
Minimum of 5 years ASIC Verification experience in a product development environment
Proven ASIC Design Verification skills
Rich experience with Specman or System Verilog
Digital verification experience on MIPS CPU/AXI/DDR Controller
Knowledge of data and telecommunication networking(IP/Ethernet)
Experience with one or more scripting languages: TCL, Perl, python
Superior debugging skills for large ASIC designs
Strong written and verbal communication skills
Adaptable to evolving customer requirement DESCRIPTION OF FUNCTION & RESPONSIBILITY:
Develop reusable block-level and system-level ASIC test benches using System verilog
Develop new ASIC verification environments to support ASIC development.
Maintain existing ASIC verification environments.
Define and develop application tests required to verify ASICs meet functional and performance goals.
Define and implement functional/code coverage plans.
Develop testing and regression methodologies for new verification flow.
Develop/maintain/enhance environment tools/scripts/makefiles.
有意者发简历给我。
desinger也可以发给我,也在招。
mail: leiyu_sc@hotmail.com