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[原创] Clock Generators for SOC Processors Circuits and Architectures

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发表于 2010-2-3 21:19:10 | 显示全部楼层 |阅读模式

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This book examines the issue of design of fully-integrated frequency synthesizers suitable for system-on-a-chip (SOC) processors. This book takes a more global design perspective in jointly examining the design space at the circuit level as well as at the architectural level. The coverage of the book is comprehensive and includes summary chapters on circuit theory as well as feedback control theory relevant to the operation of phase locked loops (PLLs). On the circuit level, the discussion includes low-voltage analog design in deep submicron digital CMOS processes, effects of supply noise, substrate noise, as well device noise. On the architectural level, the discussion includes PLL analysis using continuous-time as well as discrete-time models, linear and nonlinear effects of PLL performance, and detailed analysis of locking behavior.
The material then develops into detailed circuit and architectural analysis of specific clock generation blocks. This includes circuits and architectures of PLLs with high power supply noise immunity and digital PLL architectures where the loop filter is digitized.
Methods of generating low-spurious sampling clocks for discrete-time analog blocks are then examined. This includes sigma-delta fractional-N PLLs, Direct Digital Synthesis (DDS) techniques and non-conventional uses of PLLs. Design for test (DFT) issues as they arise in PLLs are then discussed. This includes methods of accurately measuring jitter and built-in-self-test (BIST) techniques for PLLs. Finally, clocking issues commonly associated to system-on-a-chip (SOC) designs, such as multiple clock domain interfacing and partitioning, and accurate clock phase generation techniques using delay-locked loops (DLLs) are also addressed. The book provides numerous real world applications, as well as practical rules-of-thumb for modern designers to use at the system, architectural, as well as the circuit level. This book is well suited for practitioners as well as graduate level students who wish to learn more about time-domain analysis and design of frequency synthesis techniques.

Clock Generators for SOC Processors Circuits and Architectures.part1.rar

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发表于 2010-2-3 21:20:44 | 显示全部楼层
在google看了评论,应该不错,可惜没看过
 楼主| 发表于 2010-2-3 21:25:06 | 显示全部楼层
1# netghost

Clock Generators for SOC Processors Circuits and Architectures.part2.rar

4.37 MB, 下载次数: 765 , 下载积分: 资产 -3 信元, 下载支出 3 信元

 楼主| 发表于 2010-2-3 21:28:21 | 显示全部楼层
3# netghost

Clock Generators for SOC Processors Circuits and Architectures.part3.rar

588.84 KB, 下载次数: 566 , 下载积分: 资产 -2 信元, 下载支出 2 信元

发表于 2010-2-3 21:29:55 | 显示全部楼层
发完了吗?
发表于 2010-2-3 22:31:45 | 显示全部楼层
kankan
发表于 2010-2-4 00:55:48 | 显示全部楼层
good book, thx
发表于 2010-2-4 00:57:50 | 显示全部楼层
worth learning,
thx
发表于 2010-2-4 01:00:48 | 显示全部楼层
clk div is important, thx
发表于 2010-2-4 10:20:51 | 显示全部楼层
worth learning,
thx
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