Novas-201001 (Verdi, Debussy, Siloti) Download

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To reduce unnecessary power consumption additionally, only the addressed words within a cache line are read at any time. With the required 64-bit read interface, this is achieved by disabling half of the RAMs on occasions when only a 32-bit value is required. The implementation uses two 32-bit wide RAMs to implement the cache data RAM shown in Figure 7-1 on page 7-4, with the words of each line folded into the RAMs on an odd and even basis. This means that cache refills can take several cycles, depending on the cache line lengths. The cache line length is eight words.

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The control of the level one memory system and the associated functionality, together with other system wide control attributes are handled through the system control coprocessor, CP15. Chapter 3 System Control Coprocessor describes this.

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Figure 7-1 on page 7-4 shows the block diagram of the cache subsystem. It does not show the
cache refill paths.

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The level one cache system has the following features:
1. The cache is a Harvard implementation.

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2.The caches are lockable at a granularity of a cache way, using Format C lockdown.

3.Cache replacement policies are Pseudo-Random or Round-Robin, as controlled by the RR bit in CP15 register c1. Round-Robin uses a single counter for all sets, that selects the way used for replacement.

4.Cache line allocation uses the cache replacement algorithm when all cache lines are valid. If one or more lines is invalid, then the invalid cache line with the lowest way number is allocated to in preference to replacing a valid cache line. This mechanism does not allocate to locked cache ways unless all cache ways are locked.

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5. Cache lines can contain either Secure or Non-secure data and the NS Tag, that the MicroTLB provides, indicates when the cache line comes from Secure or Non-secure memory.

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6. Cache lines can be either Write-Back or Write-Through, determined by the MicroTLB entry.

7. Only read allocation is supported.

8. The cache can be disabled independently from the TCM, under control of the appropriate bits in CP15 c1. The cache can be disabled in Secure state while enabled in Non-secure state and enabled in Secure state while disabled in Non-secure state.

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9. Data cache misses are nonblocking with three outstanding Data Cache misses being supported.

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10. Streaming of sequential data from LDM and LDRD operations, and for sequential instruction fetches is supported.

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The cache and TCM exist to perform associative reads and writes on requested addresses. The steps involved in this for reads are as follows:
1. The lower bits of the virtual address are used as the virtual index for the Tag and RAM  blocks, including the TCM.