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| On-Demand Webinar |
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| | In-Design Physical Verification for Faster Time-to-Tapeout |
| Overview:
Please join our free 45-minute webinar (including a Q&A) to learn how IC Validator, a new In-Design physical verification solution, can help speed up your tapeout schedule.
Modifying your layout after implementation can affect other designtargets such as timing, power and signal integrity. In-Design physicalverification provides a push-button flow for signoff quality metal filland Design Rule Checking (DRC) inside IC Compiler where timing canstill be considered. Our physical design and verification technologistswill show you how new IC Validator In-Design physical verificationcombines timing awareness and signoff accuracy to speed up your tapeoutschedule.
link
http://www.techonline.com/learning/webinar/217400722?queryText=synopsys
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