Charge Recycling Circuit for Leakage Power Reduction

godsnake

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Charge Recycling Circuit for Leakage Power ReductionHanh-Phuc Le (phucle @ eecs) and Jiashu Chen (jiashu@ eecs)

In recent development of lowpower digital circuits, when the technology still tries to keep its speed goingdown deep into sub-micro scale, the in-active leakage loss becomes significantof about 30% of the total power consumption, thus, can not be ignored any more.To address the problem, sleep transistor technique, as exemplarily shown inFig.1, which utilizes a high threshold transistor in series with digitalcircuits to power supply is introduced. The sleep transistor is turned on whenthe circuit is in computational mode and is turned off in standby mode toreduce leakage power consumption remarkably.

However, the virtual ground ofthe logic gates, or the drain node of the sleep transistor, which is associatedwith a relatively big parasitic capacitor, will drift up to near Vdd during standby mode due to the leakage current and thatamount of charge drawn from supply in this mode will, then, be dumped to theground when the circuit enters computational mode. This is apparently a lossthat potentially results in increasing power consumption of the circuit,especially when the mode change comes with high frequency.

In this project, we propose acharge recycling circuit that can store the charge right before thecomputational mode and dump it back to the virtual ground when the circuitenters standby mode so that the virtual ground no longer has to draw a largeamount of “leakage” charge from supply. The amount of energy that can be savedby this technique depends on several important parameters including how fastthe circuit switches between the two modes, how large the virtual groundparasitic capacitance is and how efficient the charge recycling circuit can bebuilt.

With that, our project is dividedinto two phases. First, a study will be conducted to determine the propersituation where this technique is beneficial, that most probably comes withdifferent trade-off curves including the one shown in Fig. 2. Second, anefficient charge recycling circuit will be designed to prove this idea.

登录/注册后可看大图    Fig. 1. Leakage  reduction sleep transistor

登录/注册后可看大图    Fig. 2. Power  savings trade-off

Reference:

[1]Wei, L.; Chen, Z.; Roy, K.; Johnson, M.C.; Ye, Y.; De, V.K,“Design and optimization of dual-threshold circuits forlow-voltage low-power applications” in IEEE Transactions on Volume 7, Issue 1,March 1999, pp.16 – 24.

[2]T. Kuroda, T. Fujita, S. Mita, T. Nagamatsu,S. Yoshioka, K. Suzuki, F. Sano, M. Norishima, M. Murota, M. Kako, M. Kinugawa, M. Kakumu and T. Sakurai, “A 0.9-V, 150-MHz, 10-mW, 4mm , 2-Ddiscrete cosine transform core processor with variable threshold-voltage (VT)scheme,” IEEE J. Solid-State Circuits, vol. 31, pp. 1770–1779, Nov. 1996.

[3]K. S. Min and T. Sakurai, "Zigzag Super Cut-off CMOS (ZSCCMOS) BlockActivation with Self-Adaptive Voltage Level Controller: An Alternative toClock-Gating Scheme in Leakage Dominant Era," ISSCC, pp.400-401, Feb.2003.
[4]K. S. Min and T. Sakurai, "Zigzag super cut–off CMOS (ZSCCMOS) scheme withself–saturated virtual power lines for subthreshold–leakage–suppressedsub–1–V–VDDLSI's", Proceedings of the 28thEuropean SSCC, pp.679-682, Sept.2002.

[5]E. Pakbaznia, F. Fallah and M. Pedram “Charge recycling in MTCMOS circuits:concept and analysis,” in Proc. Design Automation Conference, pp. 97-102, 2006.

[6]James Tschanz, et. al., ‘Dynamic-Sleep Transistor andBody Bias for Active Leakage Power Control of Microprocessors’, ISSCC Dig.Tech. Papers,pp 102 - 481, Feb. 2003.

[7]James Tschanz, et. al., ‘Dynamic-Sleep Transistor andBody Bias for Active Leakage Power Control of Microprocessors’, JSSC,pp 1838 - 1845, Feb. 2003.

semico_ljj

nice...

abc_def_ghi

回复 1# godsnake


    good idea