Writing Testbenches,Functional Verification of HDL Models

szj112

ding ding a dingA Practical Guide for Designing, Synthesizing, and Simulating ASICs and FPGAs using VHDL or Verilog
A Practical Guide for Designing, Synthesizing, and Simulating ASICs and FPGAs using VHDL or Verilog
A Practical Guide for Designing, Synthesizing, and Simulating ASICs and FPGAs using VHDL or Verilog

cool_snake

来赚钱，呵呵

szj112

zhao le hao jiu ding yi ge xian

wusuowei232

xie xie fen xiang

Bomber123

thanks a lot....

taohuaxian

太大了，抢钱啊

xinyanjing

多谢，多发。多顶

liang_arthur

我怎么解压不了呢？

兎兎

你要把那9个压缩包全下了 然后全选中 再點右键选解压- -##

苦海梦迷人

好多附件啊！！！