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招聘英才：
（1）IC模拟设计工程师或实习生Analog Design Engineer or trainee（数名）
A)Design consumer electronics mixed signal IC设计混合信号消费电子IC B)Responsible for product definition and micro architecture.负责产品和微结构定义 Candidates must have the following qualifications任职要求： A) M.S. Degree in EE Science. M.S. preferred.硕士学位，微电子专业 B)Recent experience of designing TFT or STN LCD driver chip is preferred.有设计TFT或STN LCD DRIVER经验优先 C)Aware of most of the issues involved including circuit design, module, glass panel, foundry interface, packaging, ESD design, testing.了解电路设计，LCD模块，LCD PANEL ,foundry , 封装，ESD 设计，测试等领域常见问题 D)Familiar with mixed signal design and verification flow.熟悉混合信号电路设计和验证流程 E)Strong analog design background and Layout experienc(LVS/DRC).具有模拟电路设计背景和需有LAYOUT 经验（LVS/DRC） F)Detailed knowledge of reference voltage circuit, dc-dc charge pump circuit, and oscillator circuit design.具备丰富reference voltage circuit, dc-dc charge pump circuit ,oscillator circuit设计知识 G)Familiar with SPICE and mixed-signal simulation tools熟悉SPICE和混合信号仿真工具
（2）ASIC逻辑设计工程师或实习生Logic Design Engineer or trainee（数名）
Job Function职责描述：
A)Design digital circuit blocks using RTL coding in mixed signal IC chips.使用RTL代码设计数字逻辑电路（用于混合信号IC）
B)Write RTL code for custom designed blocks such as SRAM and adder blocks.编写客户定制RTL代码，例：SRAM，加法器等
C)Define micro architecture of digital part of the mixed signal IC.定义混合信号IC数字部分微架构
D)Verification of the logic blocks using test bench and Vera.使用test bech和VERA语言验证逻辑功能块
E)Use FPGA to validate the designed blocks. 使用FPGA验证设计模块
F)Write synthesis script to generate gate level netlist.编写综合教本产生门级网表
G)Analyze timing for synthesized blocks.分析综合模块时序
Candidates must have the following qualifications: 任职要求：
A)1 years RTL coding experience.1年RTL代码经验
B)Understanding of concept of state-machine.了解状态机概念
C)Understanding of the concept of timing. Able to perform static timing analysis.具备时序概念，能进行静态时序分析
D)Familiar with VCS or NC-Verilog熟悉VCS 或 Verilog
E)Able to write and use test-bench to test RTL blocks.可以编写和使用测试平台测试RTL模块
F)Able to program FPGA to test logic blocks.可以使用FPGA编程测试逻辑模块
（3）IC版图设计工程师或实习IC layout Design Engineer or trainee（数名）
Job Function职责描述：
A) In charge of circuit custom layout design.
B) Responsible for block level floorplanning.
Candidates must have the following qualifications任职要求：
A) Computer Science B.S Degree in EE
B) 1 years experience in IC design.
C) Experienced in floor planning.
D) Familiar with cadence place and route tools.
E) Experienced in writing scripts for place and route.
F) Experienced in writing scripts for gate net-list synthesis.
G) Custom designed circuit layout experience.
H) Able to correctly model parasitic loading.
I) Aware of all the electric design issues involved including cross talk, IR drop, and electro-migration issues.
欢迎您的加盟！
公司地址：西安高新一路25号创新大厦N708
Email：amtsemi_hr@126.com
联系电话：029-88312307
联系人：Mr Jiao | 
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发表于 2010-1-15 14:00:33
