ESD Protection Design for High-Speed/High-Frequency I/O Interfaces

bt01234

Abstract

Electrostatic discharge (ESD) protection has been a very important reliability issue in microelectronics, especially for integrated circuits (ICs). ESD protection design for giga-Hz
high-speed input/output (I/O) circuits has been one of the key challenges to implement high-speed interface circuits in CMOS technology.
Conventional on-chip ESD protection circuits at the I/O pads often cause unacceptable performance degradation to high-speed I/O circuits. Therefore, ESD protection circuits must be designed with minimum negative impact to the high-speed interface circuits and to sustain high enough ESD robustness. In this paper, ESD protection design considerations for high-speed I/O circuits are addressed, and the patents related to on-chip ESD protection designs for high-speed I/O circuits are presented and discussed.

apteye

thanks

lyc1981

thanks

carffy

thanks

jfyan

thanks, by the way, what is type of this doc, book or paper

yuxi

thanks

air7619

thank you~

sniperbill

goodgood

chenzf

好东西 顶了  谢谢

2010.01.27

need it indeed!