With the Cadence® SoC Encounter™ RTL-to-GDSII System, engineers canaccount for the effects of interconnect across the entire chip—fromthe outset of the implementation cycle. It combines RTL synthesis,silicon virtual prototyping, automated floorplan synthesis, clocknetwork synthesis, design for manufacturability and yield, low-powerand mixed-signal design support, and nanometer routing. It also offersthe latest capabilities to support advanced 65nm and 45nm designs.
Features/Benefits
* Supports multiple implementation styles with built-in power-planning, floorplanning, and signal integrity analysis
* Supports multiple methodologies for flip-chip implementation, promoting concurrent chip/package design
* Provides a statistical static timing analysis solution and standardized ECSM library models
* Incorporates cutting-edge yield and low-power design capabilities
* Handles 50M+ gate designs at 90nm and below
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发表于 2010-1-9 09:39:30
