发一些职位（北京京芯半导体）

xiaox

联系方式  hr@capisemi.com

Mobile Communications System Architects
                        Job Description:

• Participating in all phases of L1 Modemdesign from algorithm coding to L1 Modem IP realization and L1C codingin Baseband SoC projects.
• Working with the team to design and develop high-efficient L1 Modem and/or cost-effective Baseband SoC for 3G/4G.
• Specific responsibilities include L1Modem algorithm design, simulation, FPGA prototyping, L1Cco-development, system-level simulation and testing, etc.
• Responsible for interfaces with Baseband SoC design, L1C and Protocol Stack design, and reference system design groups, etc.
  

Job Requirements:

• BSEE a must, MSEE/PhD preferred. 3+ years experience in mobile communications system design.
• Hands-on experience in 3G/4G L1 algorithm design and development.
• Familiar with L1 Modem coding, simulation, and prototyping flow.
• Solid background in WCDMA/HSPA/LTE algorithm designs and implementation
• Well understanding about H/W and S/W partitioning and trade-offs
• Familiar with computer architecture, DSP design, and/or mobile Baseband SoC architecture and low-power design are a plus.
• Mobile platform level exposure and knowledge of modem and network protocols and software are a plus
• Good communication skills in both Chinese and English.
• Good team work spirit.
  

                               

Senior Baseband SoC Design Engineers  

                        Job Description:

• Participating in all phases of mobile Baseband SoC design from RTL coding to FPGA prototyping, and silicon debug and testing.
• Working with the team to design and verify high efficient L1 Modem IP and to develop low-power mobile Baseband SoC for 3G/4G.
• Specific responsibilities include logicdesign, synthesis, top-level integration, test plans and test suitesdevelopment, full-chip simulation and functional test vectorgenerations.
• Responsible for interfaces with physical design team and system design group.
  

Job Requirements:

• BSEE a must, MSEE preferred. 3+ years experience in Baseband SoC design.
• Hands-on experience in RTL (Verilog preferred) and design verification.
• Familiar with RTL coding and verification/synthesis flow.
• Solid background in WCDMA/HSPA/LTE mobile Baseband SoC and low-power designs
• Familiar with computer architecture, DSP/microprocessor design, and/or video/audio/3D applications processing design are a plus.
• Good communication skills in both Chinese and English.
• Good team work spirit.
  

Senior Baseband SoC Design Verification Engineers  





                        Job Description:

• Responsible for the development of a verification environment and test suites for full chip and block level.
• Developing functional test/verification plan for L1 Modem IP and mobile Baseband SoC
• Responsible for ASIC test vectors generation and debugging.
• Working with system and hardwareengineers to port the tests to other environments (such as FPGAprototyping systems), silicon bring up and validation, etc.
  

Job Requirements:

• BSEE a must, MSEE preferred. 3+ years experience in Baseband SoC design verification
• Experience in verifying designs at system level and block level is required
• Solid background in WCDMA/HSPA/LTE L1 Modem and/or mobile Baseband SoC design verifications experience
• Experience with either ARM or DSP embedded architectures is preferred.
• Strong Verilog, Vera, PERL, TCL, and C programming skills.
• Good communication skills in both Chinese and English.
• Good team player and self-motivated.
  

ASIC Design and Verifications Engineers

                        Job Description:

• The responsibility includes logic design, design validation, synthesis, static timing analysis and formal verification.
• Responsible for structured scan insertion, MBIST, and boundary scan implementation.
• Working closely with other teams to ensure the design quality for successful tapeout.
  

Job Requirement:

• BSEE a must, MSEE preferred, with 0-3 years experience in IC design and verifications
• Hands-on experience on Verilog RTL design, development, and debug
• Familiar with verilog design simulation, synthesis, static timing analysis, and formal verification flows and Synopsys tools.
• good background in WCDMA/HSPA/LTE L1 Modem and/or mobile Baseband SoC design and verifications experience are a strong plus
• DFT concepts of Scan, BIST, and LogicBIST.
• C/C++, Perl, and Tcl programming skills are a strong plus.
• Good communication skills in both Chinese and English.
• Good team player and self-motivated.  
  
  

Physical Design Engineers  

                        Job Description:

• Responsible for floor planning, power planning, place&route, timing analysis, physical verification (DRC/LVS/ERC/ANT);
• The electronic concerns, such as signalintegrity, power IR drop analysis, noise analysis, and ElectroMigration analysis are also within the scope.
  

Job Requirement:

• BSEE a must, MSEE preferred, with 2+ years experience in IC backend design.
• Hands on experience with Synopsys, Cadence, or Magma Place&Route tools, physical verification tools and STA.
• Knowledge of RC extraction, timing analysis, signal integrity, and physical verification (DRC/ERC/LVS/ANT) is required.
• C/C++, Perl, and Tcl programming skills are a strong plus.
• Good communication skills in both Chinese and English.
• Good team player and self-motivated.  
  
  

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