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发表于 2009-12-12 13:40:55
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because the number of MOS devices in PLL is very large(if your PLL is complex
especialy for multistage ring vco and divider ckt)
if you do not run pll behavior simulation firstly then it will take
very long time to run simulation in hspice and if
the result is error then you will try again and it takes a lot of time and try and error
(2)the PLL behavior simulation can be done with simulink and matlab equation
matlab equation can be used to simulate the phase margin of pll(bode plot diagram)
the simulink behavior of pll can be used to run trainsinet behavior simulation of pll.
The purpose of behavior simulation is to help you quickly determine vco gain ,charge pump current ,loop filter value to find out if your pll locking time ,stablity etc can meet the spec
(3)The PLL transistor level simulation can be done with hspice (the most accurate)
but it will take a lot of time(such as several days)
so you can run the PLL transistor level ckt with nanosim(it is faster than hspice but it will
take less time (such as several hours)than hspice but the accuracy of nanosim is not as hspice
Any way the final result must be verfied with hspice
but you can do pll behavior simulation firstly with matlab ,simulink then use nanosim to do PLL transistor level ckt to get roughly result and finally using hspice to get the most accurate result! |
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