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This application note provides design
guidelines for clock trees so as to
facilitate and optimize their automatic
processing by place and route.
The information in this application note is
independent of the CAD tool used.
A minimum knowledge of design methodology
is required before reading this
document.
When generation of a clock tree is
required, the clock net must be identified
to the place and route tool so that any
special handling is carried out correctly.
Moreover, in order to enable correct prelayout
back-annotated simulation, a special
library element must be associated
with the clock net.
This element, the clock tree prebuffer
cell (ctprebuff), can be placed at any
level of hierarchy in the design.
This application note gives guidelines as
to the use of the ctprebuff cell and examples
are given for simple balanced clock
trees, unbalanced trees, multiple clock
trees and gated clocks.
In all cases, it is important to note that
any special processing required during
place and route must be identified in
advance. |
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eetop公众号
创芯大讲堂
创芯人才网
发表于 2009-11-15 09:21:08
