TUTORIAL: CADENCE DESIGN ENVIRONMENT

hi_china59

TUTORIAL: CADENCE DESIGN ENVIRONMENT

1. INTRODUCTION.....................................................................................4
2. ANALOG IC DESIGN FLOW AND REQUIRED TOOLS....................................4
3. SETTING YOUR UNIX ENVIRONMENT........................................................5
4. RUNNING CADENCE................................................................................6
5. ANALOG DESIGN WITH CADENCE DESIGN FRAMEWORK II.........................8
5.1. Library Creation and Selection of Technology..........................................8
5.2. Schematic Entry with Composer............................................................9
  5.2.1. Symbol Creation.............................................................................11
  5.3. Simulation........................................................................................13
  5.3.1. Setting simulator............................................................................14
  5.3.2. Setting models...............................................................................14
  5.3.3. Setting design variables...................................................................14
  5.3.4. Selecting the analysis......................................................................15
  5.3.5. Running the simulation....................................................................15
  5.3.6. Plotting the simulation results..........................................................15
  5.4. Layout..............................................................................................17
  5.4.1. Basic Full-Custom Layout.................................................................20
  5.4.2. Full custom layout using pcells..........................................................29
  5.4.3. Fill-custom layout using Virtuoso XL..................................................31
  5.4.4. Hierarchical layout...........................................................................33
  5.5. Verification........................................................................................33
  5.5.1. Design Rule Check (DRC).................................................................33
  5.5.2. Layout versus Schematic (LVS)........................................................35
  5.6. Post-Layout simulation......................................................................39
6. TRANSFER TO FOUNDRY............................................................ ...........40
7. PRINTING IN CADENCE................................................................  .........42
8. REFERENCES............................................................................ ...........45
APPENDIX: ADVANCED TOPICS
  A.1. TRANSITION GUIDE FROM TANNER TOOLS TO CADENCE.......................47
  A.2. INTRODUCTION TO SKILL..................................................................50
A.3. LOGIC SIMULATION WITH VERILOG...................................................52

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1# hi_china59

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15215127296

回复 1# hi_china59


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