【【职位更新啦！！---DFT /Design /Verification等等】】~~世界知名芯片公司

robin_li

Title:                   DFT Engineer (3 H/C)
Location:       Shanghai

PREFERRED EXPERIENCE:
1. Master of EE or above. 2+ years DFT experience.
2. Prove million gates DFT project experience, and can handle complex DFT design independently.
3. Knowledge of Digital design, IC design methodology and Concepts of design for test
4. Strong abilities of solving timing or other DFT related issues with integration and PD team.
5. Be familiar with verilog language
6. Be familiar with Unix and TCL, cshell , Perl scripts.
7. Good Englisth communication skills
8. Self-motivated and good team player

Title:                   DFT Engineer (4 H/C)
Location:             Shanghai

PREFERRED EXPERIENCE:
1.    Master of EE or above. 2+ years  DFT experience.
Experience in complex ASIC Design Verification, experience in handling big SOC designs.
2.    Knowledge about the industrial standard DFT/BIST/JTAG/MBIST methodology or technology as well as knowledge about ASIC testers and ATPG.
3.    Working knowledge of verilog and experience in verilog simulator and waveform debugging tools.
4.    Experience with SystemC/C/C++/SystemVerilog and the use of hardware assertion languages such as PSL/SVA.
5.    Knowledge of coverage-driven verification methodology.
6.    Good debugging capability with both RTL and gatelevel simulations.
7.    Good communication skills and the ability and desire to work as a team.

Title:                    Senior Design Verification Engineer for Video Codec
Location:             Shanghai
Preferred Experience:
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Major in CS or EE and have Master degree or higher
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3 years beyond working experience on ASIC design verification
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Must have strong background on video encoding/decoding algorithms
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Must be proficient in C++ programming and debugging in Linux and Windows platforms. Know well about SW engineering.
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Must be experienced in various verification methodologies from block level to SoC level, and familiar with corresponding tools.
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Must be skillful in shell/perl/tcl/Makefile programming in linux OS.
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Should have adequate ASIC design knowledge and be able to debug RTL codes using corresponding tools
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Good English hearing, speaking, reading and writing capabilities.
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Will be a big plus if having tape‐out experience.


JOB TITLE:

Senior Design Engineer for Video Codec
Preferred Experience:
-
Major in EE and have Master degree or higher
-
3 years beyond working experience on ASIC design
-
Must have strong background on video encoding/decoding algorithms
-
Must be proficient in Verilog coding, debugging and modeling
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Must be skilled in ASIC design flow, such as synthesis, DFT, timing analysis, ECO etc.
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Must be skilled in mainstream EDA tools for design and simulation such as ncsim/vcs, RC/DC, PT, Formality/LEC and DFT.
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Must be familiar with verification methodologies for from block level to SoC level.
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Should be familiar with shell/perl/tcl programming in linux OS.
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Should be familiar with P&R and Manufacture tech.
-
Good English hearing, speaking, reading and writing capabilities.
-
Will be a big plus if having tape‐out experience.
Will be a plus if having C/C++, matlab experience



职位还有很多很多，大家感兴趣可以跟我联系了解详细职位信息

E-mail & MSN : milujite@msn.com

robin_li

up  up  up~~~~~~~~~

reniss

啥子公司?在上海哪里?....最好能有点公司介绍

robin_li

公司在上海张江~~~

robin_li

up   up   up~~~~~~~~~~~~^^^^^^^^^^^^

robin_li

DING~~~DING~~************

robin_li

up    up    up~~~~~~~~

hitten

这年头是不是玩DFT的人不多啊，怎么应届的也要？

scsdyxf

good?

robin_li

职位招聘继续~~~~~~~~~~~