Asynchronous system-on-chip interconnect

cirand · 发表于 2009-10-11 22:31:26

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异步电路设计的一份博士论文，后已出版成书，希望对做异步电路的朋友有用。
Chapter 1: Introduction ....................................................................................13
1.1 Asynchronous design and its advantages ...............................................14
1.1.1 Avoidance of clock-skew .............................................................15
1.1.2 Low power ...................................................................................15
1.1.3 Improved electro-magnetic compatibility (EMC) ........................16
1.1.4 Modularity ....................................................................................16
1.1.5 Better than worst-case performance .............................................17
1.2 Disadvantages of asynchronous design ..................................................18
1.2.1 Complexity ...................................................................................18
1.2.2 Deadlock ......................................................................................18
1.2.3 Verification ..................................................................................18
1.2.4 Testability .....................................................................................19
1.2.5 “It’s not synchronous” .................................................................19
1.3 Thesis Overview .....................................................................................19
1.4 Publications ............................................................................................22
Chapter 2: Asynchronous Design .....................................................................23
2.1 Introduction ............................................................................................23
2.2 Asynchronous design ..............................................................................25
2.2.1 Circuit classification ....................................................................25
2.2.2 The channel ..................................................................................26
2.2.3 Signalling conventions .................................................................27
2.2.4 Data representation ......................................................................29
2.2.5 The Muller C-element ..................................................................32
2.2.6 Specifications and automated circuit synthesis ............................32
2.2.7 Metastability, arbitration and synchronisation .............................35
2.2.8 Sutherland’s micropipelines .........................................................36
2.2.9 Large Asynchronous Circuits .......................................................38
2.3 Summary .................................................................................................40
Chapter 3: System Level Interconnect Principles ...........................................41
3.1 Point-to-point communication paths ......................................................41
3.2 Multipoint interconnect topology ...........................................................42
3.2.1 Shared buses .................................................................................42
3.2.2 Star and Ring Networks ...............................................................42
3.2.3 Meshes .........................................................................................42
3.3 Bus protocol issues .................................................................................43
3.3.1 Serial operation ............................................................................44
3.3.2 Multiplexed address/data lines .....................................................44
3.3.3 Separate address and data lines ....................................................44
3.3.4 Arbitration ....................................................................................45
3.3.5 Atomic sequences ........................................................................46
3.3.6 Bursts ...........................................................................................46
3.3.7 Interlocked or decoupled transfers ...............................................46
3.3.8 Split transactions ..........................................................................46
3.4 Interconnect performance objectives ......................................................47
3.5 Commercial on-chip buses .....................................................................47
3.5.1 Peripheral Interconnect Bus (PI-Bus) ..........................................48
3.5.2 The Advanced Microcontroller Bus Architecture (AMBA) ........48
3.5.3 CoreConnect .................................................................................49
3.6 Summary .................................................................................................51
Chapter 4: The Physical (Wire) Layer .............................................................52
4.1 Wire theory .............................................................................................53
4.2 Electrical and physical characteristics ....................................................54
4.3 Termination ............................................................................................55
4.4 Crosstalk .................................................................................................55
4.4.1 Propagation delay for well separated wires .................................58
4.4.2 Signal propagation delay with close-packed wires ......................58
4.4.3 Alternative wiring arrangements ..................................................59
4.5 Summary .................................................................................................64
Chapter 5: The Link Layer ...............................................................................65
5.1 Centralised vs distributed interfaces .......................................................66
5.2 Signalling Convention ............................................................................67
5.3 Data Encoding ........................................................................................67
5.4 Handshake sources .................................................................................68
5.5 Bidirectional data transfer ......................................................................69
5.6 Multiple initiators on one channel ..........................................................70
5.6.1 Arbitration ....................................................................................71
5.6.2 Request drive and hand-over ........................................................77
5.6.3 Push data drive and hand-over .....................................................78
5.6.4 Transfer deferral/hardware retry ..................................................79
5.6.5 Atomic transfers and locking .......................................................81
5.7 Multiple Targets .....................................................................................83
5.7.1 Acknowledge drive and hand-over ..............................................83
5.7.2 Target selection ............................................................................84
5.7.3 Decode and target exceptions ......................................................85
5.7.4 Pull data drive and hand-over ......................................................85
5.7.5 Defer .............................................................................................86
5.8 Multipoint bus-channel interfaces ..........................................................86
5.9 MARBLE’s Link Layer Channels ..........................................................88
5.10 Summary ...............................................................................................89
Chapter 6: Protocol Layer .................................................................................90
6.1 Transfer phases .......................................................................................91
6.1.1 The command phase .....................................................................91
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6.1.2 The acknowledge phase ...............................................................92
6.1.3 The data phase ..............................................................................92
6.1.4 The response phase ......................................................................92
6.2 Exceptions ..............................................................................................93
6.3 Defer and bridging ..................................................................................94
6.4 Mapping transfer phases onto channel cycles ........................................94
6.4.1 Sequential operation using a single channel ................................95
6.4.2 Parallel operation using multiple channels ..................................97
6.5 Transfer cycle routing .............................................................................98
6.5.1 Interlocked protocols ....................................................................99
6.5.2 Decoupled protocols ..................................................................100
6.6 Transfer cycle initiation ........................................................................101
6.7 MARBLE’s dual channel bus architecture ...........................................103
Chapter 7: Transaction Layer ........................................................................104
7.1 Split transactions ...................................................................................105
7.1.1 Split transactions give better bus availability ............................106
7.1.2 Implementation on an interlocked protocol layer ......................106
7.1.3 Implementation on a decoupled protocol-layer .........................108
7.2 Response ordering ................................................................................109
7.2.1 Single outstanding command .....................................................111
7.2.2 Multiple outstanding commands and pipelining ........................112
7.2.3 Number of outstanding commands ............................................113
7.2.4 A grouping of single outstanding command interfaces .............113
7.2.5 Sequence tagging and reordering of responses ..........................115
7.3 MARBLE’s Transaction Layer ............................................................118
Chapter 8: MARBLE: A dual channel split transfer bus ............................119
8.1 MARBLE protocol and signal summary ..............................................119
8.1.1 Two channels .............................................................................120
8.1.2 Split transactions ........................................................................122
8.1.3 Exceptions ..................................................................................122
8.1.4 Arbitration ..................................................................................122
8.1.5 Atomic transactions and locking ................................................123
8.1.6 Burst optimisation ......................................................................123
8.2 Bus transaction interface implementation ............................................124
8.2.1 Interface structure ......................................................................125
8.2.2 Data storage and manipulation ...................................................126
8.2.3 Token management ....................................................................129
8.3 MARBLE in the AMULET3H System ................................................130
8.3.1 The AMULET3 Processor Core ................................................131
8.3.2 RAM ...........................................................................................132
8.3.3 ROM ...........................................................................................133
8.3.4 DMA Controller .........................................................................134
8.3.5 External Memory/Test Interface ................................................134
8.3.6 ADC/AEDL ...............................................................................134
8.3.7 SOCB .........................................................................................135
8.3.8 Instruction bridge and local bus .................................................137
8.3.9 Data bridge and local bus ...........................................................138
8.4 Summary ...............................................................................................139
Chapter 9: Evaluation ......................................................................................141
9.1 The MARBLE testbed ..........................................................................142
9.2 Simulation of MARBLE in AMULET3H ............................................142
9.2.1 Single initiator to single target ...................................................144
9.2.2 Two initiators accessing different targets ..................................145
9.2.3 Two initiators accessing the same target ....................................146
9.2.4 Three Initiators accessing different targets ................................147
9.3 Analysis of delay distribution ...............................................................151
9.3.1 Centralised and Distributed Decoding .......................................152
9.3.2 Arbitration ..................................................................................152
9.3.3 Data drive setup time .................................................................153
9.3.4 Pipeline latch controller delays ..................................................154
9.3.5 Sender activity ............................................................................155
9.3.6 Performance summary ...............................................................155
9.4 Hardware requirements .........................................................................156
9.5 Comparison with synchronous alternatives ..........................................156
Chapter 10: Conclusion ...................................................................................158
10.1 Advantages and disadvantages of MARBLE .....................................159
10.1.1 Increased modularity ................................................................159
10.1.2 Avoidance of clock-skew .........................................................160
10.1.3 Low power consumption ..........................................................160
10.1.4 Improved electro-magnetic compatibility (EMC) ....................160
10.1.5 Performance .............................................................................161
10.1.6 Risk of deadlock .......................................................................161
10.1.7 Timing verification ..................................................................161
10.1.8 Design complexity ...................................................................162
10.1.9 Reliable arbitration ...................................................................162
10.2 Improving the MARBLE bus .............................................................163
10.2.1 Separating the read and write data paths ..................................163
10.2.2 Less conservative drive overlap prevention .............................164
10.2.3 Allowing multiple outstanding commands ..............................164
10.3 Alternative interconnect solutions and future work ...........................165
10.3.1 Changing the interconnect topology ........................................165
10.3.2 Changing to a delay-insensitive data encoding ........................166
10.4 The future of asynchronous SoC interconnect? ..................................168
Appendix A: MARBLE Schematics ...............................................................169
A1 Bus Interface Top Level Schematics ....................................................169
A2 Initiator Interface Controllers ...............................................................170
A3 Target Interface Controllers ..................................................................172
A4 Bus drivers and buffers .........................................................................173
A5 Latch controllers ...................................................................................174
A6 Centralised bus control units ................................................................176
References ........................................................................................................179

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