quartus II 中调用宏模块ALTCLOCKLOCK ?

huashi911

我使用altera的APEX20KE的器件, 现在我想在quartus II中调用其中的一个宏模块
'altclocklock'时钟琐相这个模块,以实现输入时钟的2分频和4分频输出
可是,调用后在quartus II中运行编译一直出错，提示只能有一个输出
在该器件的资料里显示可以双时钟输出的,请问这是什么原因?
同时,我让一个口输出后,时钟的相位和输入时钟相位不在一起
有一些负延时,怎么可以消除,PLL 应该可以保证相位的一致的....
请大家给些意见...谢谢了

serene

In APEX 20K devices, if the pin driving the inclock port of the PLL is used elsewhere in the design, you can use only the clock0 output port of the PLL. No fit is possible if you simultaneously use the clock0 port, clock1 port, and the pin driving the inclock port of the PLL.

huashi911

of course , that is in apex20k devices, but in apex20ke devices you can use any two of the clock0 port, clock1 port, and the pin driving the inclock port of the PLL.

harry1862pd

thank you very much