Via内部STA脚本代码

wz_cdj

Via内部STA脚本代码，本人不发骗人的帖子，信不信由你

jhw

........................

xhhe

好东西啊

xhhe

谢谢分享。但我怎么下不下来呢

cjchang1

Thanks a lot !!!!!!!!!!!!!!!

lufeng21cn

学习了.谢谢

daidaihou

好啊啊啊啊啊啊

smezsc

谢谢楼主啊！

rsheile

谢谢楼主分享哦！

binglingxiao

remove_design -all
#=============================================
#set environment variable
#=============================================
set link_create_black_boxes false
set timing_clock_reconvergence_pessimism normal
set timing_remove_clock_reconvergence_pessimism true
set svr_keep_unconnected_nets false
set timing_slew_propagation_mode worst_slew
set case_analysis_sequential_propagation always
suppress_message PARA-023
#=============================================
#set search_path and slow.db as link_library
#=============================================
set search_path "~/uwbm_case/techlibs/acisc/synopsys"
set target_library "~/uwbm_case/techlibs/acisc/synopsys/slow.db"

#set link_library [concat * $target_library ]
set link_library " * ~/uwbm_case/techlibs/acisc/synopsys/slow.db"


#==========================================================
# Read verilog and set the uwbm_rcvy_chip as current design
#==========================================================
read_verilog ~/uwbm_case/flowstep/par/work/uwbm_rcvy_chip.v
current_design uwbm_rcvy_chip
link
#===============list lib===================================
list_lib
#================================================================
# set operation condition
#================================================================
set_operating_condition -analysis_type on_chip_variation -library slow  slow

#================================================================
# Read SPEF
#================================================================
#read command
read_parasitics -format SPEF -complete_with ZERO ~/uwbm_case/flowstep/rcxt/work/uwbm_rcvy_chip.max.spef

#report parasitcis annotating percent
report_annotated_parasitics -check -list_not_annotated  -constant_arcs

#================================================================
#set constraint
#================================================================
# set the condition of analyzing normal function timing by set_case_analysis command
set_case_analysis 0 test_scan_mode
set_case_analysis 0 test_scan_en
set_case_analysis 0 test_scan_di

#set clock constraints such creating clock and seting uncertainty
create_clock -n mclk  -p 10                 [get_ports mclk ]
#create_clock -n mrst_ -p 10                 [get_ports mrst_]

set_clock_transition        -min        0.05          [get_clocks mclk]
set_clock_transition        -max        0.1           [get_clocks mclk]

set_clock_uncertainty        -setup  0.05      [get_clocks mclk]
set_clock_uncertainty        -hold   0.05      [get_clocks mclk]

#set ports constraint such as input delay and output delay, driver and load
# set_drive 0 [get_ports mrst_]
# set_drive 0 [get_ports mclk ]
# set_ideal_network [get_ports mclk mrst_]
set_dont_touch_network [get_ports "mclk mrst_" ]
set_driving_cell -lib_cell DFFX4 -pin Q  [get_ports "mclk mrst_"]
set_driving_cell        -lib_cell DFFX4 -pin Q [remove_from_collection [all_inputs] [get_ports mclk ] ]
set_load         [expr [load_of  slow/AND2XL/A]*4  ]                       [all_outputs]

set_input_delay            -min    1          -clock mclk         mrst_
set_input_delay            -max    2          -clock mclk         mrst_
set_input_delay            -min    1  -clock mclk         [remove_from_collection [all_inputs] [get_ports mclk ] ]
set_input_delay            -max    2  -clock mclk    [remove_from_collection [all_inputs] [get_ports mclk ] ]
set_output_delay    -min    0.5         -clock mclk         [all_outputs]
set_output_delay    -max    1          -clock mclk         [all_outputs]

#set setup and hold constraint of gating clock
set_clock_gating_check -setup 0.2 -hold 0.2  [get_ports mclk ];

#=====================================================================
# propagate clock path delay
#=====================================================================
set_propagated_clock [all_clocks]

#=====================================================================
# Adjust PVT making use of set_timing_derate command
#=====================================================================
set_timing_derate -early 0.95
set_timing_derate -late  1.05

#=====================================================================
# check design validation
#=====================================================================
# report ecception information such as flase path
report_exception

# reports case analysis entries on ports and pins
report_case_analysis

# report disable timing
report_disable_timing

#==========================================================
# Read verilog and set the uwbm_rcvy_chip as current design
#==========================================================
# check timing
check_timing

#displays attributes on the current_design by report_design
report_design

#reports the design hierarchy by report_hierarchy
report_hierarchy

#======================================================================
# report design clock constraint validation
#======================================================================
#report clock information
report_clock

#=======================================================================
# timing analysis
#=======================================================================
#report all
report_constraint -all_violators

#report about coverage of timing checks
report_analysis_coverage

#report timing including net,transition capacitor input pin 5bits significant digits
report_timing -nets -transition_time -capacitance -input_pins -significant_digits 5
               
#=======================================================================
# output data
#=======================================================================
#write sdf
write_sdf       -no_edge -version 1.0    ./CDJSTA.sdf

#write sdc
write_sdc       ./CDJSTA.sdc

#========================
# precise
#========================

report_timing -group **async_default** -delay min
report_timing -group **async_default**

report_timing -group **clock_gating_default**
report_timing -group **clock_gating_default** -delay min

report_timing -group mclk

report_timing -from wave_data_regs_reg_19/CK -to uwbm_data_rcvy/rcvy_data_fail_reg/D

remove_clock_uncertainty

   179  get_alternative_lib_cells *TLATNXL*
   180  get_alternative_lib_cells *TLATN*
   181  get_alternative_lib_cells LOCKUP
   182  report_alternative_lib_cells LOCKUP
   183  size_cell LOCKUP TLATNX2
   184  report_analysis_coverage
   185  report_timing
   186  size_cell LOCKUP TLATNX4
   187  report_timing
   188  report_alternative_lib_cells LOCKUP
   189  report_bottlneck
   190  report_bottleneck
   191  report_alternative_lib_cells uwbm_rcvy_mfsm/U12
   192  report_alternative_lib_cells uwbm_rcvy_mfsm/U10
   193  report_alternative_lib_cells uwbm_rcvy_mfsm/U10uwbm_data_rcvy/mclk_r_REG12_S14
   194  report_alternative_lib_cells uwbm_data_rcvy/mclk_r_REG12_S14
   195  size_cell uwbm_data_rcvy/mclk_r_REG12_S14 slow/DFFRHQX4
   196  report_timing
   197  report_timing
   198  report_timing
   199  report_timing
   200  size_cell uwbm_data_rcvy/mclk_r_REG12_S14 slow/DFFRHQX4size_cell uwbm_data_rcvy/mclk_r_REG12_S14 slow/DFFRHQX4
   201  history

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