vcs 的一个bug

BABABA · 发表于 2009-9-11 17:05:17

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在跑仿真的时候，当从一个RAM中读取数据时，发现数据不对。

仔细检查了写入的数据和地址，没错。
但是读出相应地址的数据时，会出错，数据不符合写入的值。

后来在always block里的读操作后面加了一个display的语句，结果读出的数据就对了。
这是否跟vcs仿真算法有关？

怀疑这是vcs的一个bug，不知是否如此。
可有哪位大牛出来指点指点？介绍个vcs相关的文档看看，理解理解vcs仿真的process。多谢多谢

humann · 发表于 2009-9-11 17:31:07

It isn't very surpirise that you found only A vcs bug. I found A LOT and reported them to synopsys support centrum.
However, They fixed bugs quite quickly and vcs is the best simulator for systemverilog I've used.

BABABA · 发表于 2009-9-11 18:31:40

原帖由 humann 于 2009-9-11 17:31 发表

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It isn't very surpirise that you found only A vcs bug. I found A LOT and reported them to synopsys support centrum. However, They fixed bugs quite quickly and vcs is the best simulator for systemver ...

i m rookie,bugs visit rookie not much...

so, bugs' lover,
have you ever encountered the problem that i mentioned?