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1>Senior Design Engineer for Video Codec
Preferred Experience:
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Major in EE and have Master degree or higher
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3 years beyond working experience on ASIC design
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Must have strong background on video encoding/decoding algorithms
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Must be proficient in Verilog coding, debugging and modeling
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Must be skilled in ASIC design flow, such as synthesis, DFT, timing analysis, ECO etc.
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Must be skilled in mainstream EDA tools for design and simulation such as ncsim/vcs, RC/DC, PT, Formality/LEC and DFT.
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Must be familiar with verification methodologies for from block level to SoC level.
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Should be familiar with shell/perl/tcl programming in linux OS.
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Should be familiar with P&R and Manufacture tech.
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Good English hearing, speaking, reading and writing capabilities.
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Will be a big plus if having tape‐out experience.
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Will be a plus if having C/C++, matlab experience
Location:Shanghai
2>Senior Design Verification Engineer for Video Codec
Preferred Experience:
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Major in CS or EE and have Master degree or higher
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3 years beyond working experience on ASIC design verification
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Must have strong background on video encoding/decoding algorithms
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Must be proficient in C++ programming and debugging in Linux and Windows platforms. Know well about SW engineering.
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Must be experienced in various verification methodologies from block level to SoC level, and familiar with corresponding tools.
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Must be skillful in shell/perl/tcl/Makefile programming in linux OS.
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Should have adequate ASIC design knowledge and be able to debug RTL codes using corresponding tools
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Good English hearing, speaking, reading and writing capabilities.
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Will be a big plus if having tape‐out experience.
Location:Shanghai
3>Sr. Physical Design Engineer
PREFERRED EXPERIENCE:
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PhD with 1+ years of industrial experience or MSEE with 3+ years of industrial experience in ASIC design
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Expertise in place and routing, signal integrity, power analysis, CTS design, DFT, design rule and connectivity verification, timing closure.
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Successfully gone through complete product development cycle. Good analytical and debugging skills
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Good listening, writing and speaking English.
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Good communication skills, strong interpersonal skills and the flexibility. Dedicated, hard working and good team player
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Familiar with Back-End (physical design) EDA tools (synopsys,cadence,magma)
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Familiar with Front-End EDA tools or circuit design is a plus
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Familiar with Unix/Linux environment and good at scripts
LOCATION: Shanghai
4>Sr/MTS ASIC Design/Integration Engineer
PREFERRED EXPERIENCE:
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MSEE or PhD and CGPA of 8.0 out of 10.0 or higher with minimum 2-3 years of ASIC design and integration experience is required.
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Familiar with complex high speed ASIC Design process.
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Relevant experience in Graphics, Memory Controller (DDR, DDR2, DDR3), Video, Microprocessor Design, SOC design is a plus.
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Relevant experience in bus protocol USB/PCI/PCIE design is a plus.
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Relevant experience in chip level design/integration, DFT, memBIST, Memory Compiler, STA is a plus.
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Strong logic design, verification and debugging skills.
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Exposure to Digital systems and VLSI design, Computer Architecture, Computer Arithmetic, and C/C++ programming languages, CMOS transistors and circuits is optional.
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Good communications skills and ability and desire to work as a team player are a must.
LOCATION: Shanghai
大家要是感兴趣可以跟我联系哦@_@
E-mail & MSN : milujite@msn.com
[ 本帖最后由 robin_li 于 2009-9-24 09:38 编辑 ] |
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发表于 2009-8-21 09:47:21
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