|
马上注册,结交更多好友,享用更多功能,让你轻松玩转社区。
您需要 登录 才可以下载或查看,没有账号?注册
x
内部推荐!
我是Hardware Engineer, 目前本部门招聘Senior Logic Design Verification Engineer,这个职位直接report给美国的ASIC部门,配合开发NP,Switch,的ASIC或者FPGA。
关于Force10 Networks, 请访问 www.force10networks.com,公司在张江碧波路上。
有意者,请发送你的邮件至我的信箱:wong_meng@hotmail.com, 或者联系我的MSN wong_meng@hotmail.com
Senior Logic Design Verification Engineer
Job Description:
Become an integral member of Force10 Networks Logic Design Team, working as a individual contributor, providing technical leadership and expertise, developing logic design verification strategies and methodologies for intellectual property (IP) cores and networking chipsets.
Responsibilities:
 Responsible for the ASIC and FPGA design verification;
 Definition and execution of design verification plans;
 Debug of failing test cases and report test coverage metrics;
 Participation in lab bring-up, debug, and validation of final products.
Requirements:
 MS in EE/CSE with 4+ years experience or BS in EE/CSE with 6+ years experience in ASIC/FPGA design and verification using industry-standard EDA tools;
 Must have good communication and inter-personal skills, Good command of English, both Oral and Written;
 Ability and desire to foster a team environment.
Skills of the perfect candidate:
 Good Verilog coding skills is required.
 Capability of generating test bench, developing test plan, and writing direct and random tests according to design spec is required;
 Good working knowledge of Ethernet protocols is required.
 Unix/Perl/VCS/C/C++ proficiency is required;
Other desired skills:
 Experience with Hardware Verification Languages (HVL) like VERA or systemC is a plus.
 Knowledge of network traffic management and packet buffering is a plus;
 Source code control system knowledge like Perforce is a plus.
 Assertion-based verification is a plus;
 Proficiency in Makefiles and UNIX scripting languages (PERL, tcl, csh, sh) is a plus;
Knowledge of internetworking and telecommunication standards is a plus;
[ 本帖最后由 rockywangsdc 于 2009-8-13 14:30 编辑 ] |
|