ST--Clock Dividers Made Easy

pinder

ST 公司的 Clock Dividers Made Easy 资料，英文的。
讲怎么从已有时钟分出 50% 占空比的各种时钟，包括奇数分频，小数分频。
里面有波形图、门级的原理图，讲的比较清楚。

摘要如下

ABSTRACT
Dividing a clock by an even number always generates 50% duty cycle output.
Sometimes it is necessary to generate a 50% duty cycle frequency even when
the input clock is divided by an odd or non-integer number.
This paper talks about implementation of unusual clock dividers.
The paper starts up with simple dividers where the clock is divided by an odd number (Divide by
3, 5 etc) and then later expands it into non-integer dividers (Divide by 1.5, 2.5 etc). The circuits
are simple, efficient and are cheaper and faster than any external PLL alternatives. This paper
also covers Verilog code implementation for a non-integer divider.

armweak

这个比较适合初学者。

raulqql

thanks a lot

sycall

good paper

sspa

谢谢分享

fengchuhua

工作频率怎么样呢？

fengchuhua

工作频率怎么样呢？

keilwang

kankan

haoyachuan

学习一下，谢了

fengchuhua

看看怎么样，先谢了