(ebook)SystemVerilog for Design(Second Edition)

mscyc0909 · 发表于 2010-8-21 16:42:35

Topics covered:
This book focusses on the portion of SystemVerilog that is intended for representing
hardware designs in a manner that is both simulatable and synthesizable.

Chapter 1 presents a brief overview of SystemVerilog and the key enhancements that
it adds to the Verilog language.

Chapter 2 discusses the enhancements SystemVerilog provides on where design data
can be declared. Packages, $unit, shared variables and other important topics regarding
declarations are covered.

Chapter 3 goes into detail on the many new data types SystemVerilog adds to Verilog.
The chapter covers the intended and proper usage of these new data types.

Chapter 4 presents user-defined data types, a powerful enhancement to Verilog. The
topics include how to create new data type definitions using typedef and defining
enumerated type variables.

Chapter 5 looks at using structures and unions in hardware models. The chapter also
presents a number of enhancements to arrays, together with suggestions as to how
they can be used as abstract, yet synthesizable, hardware modeling constructs.

Chapter 6 presents the specialized procedural blocks, coding blocks and enhanced
task and function definitions in SystemVerilog, and how these enhancements will
help create models that are correct by design.

Chapter 7 shows how to use the enhancements to Verilog operators and procedural
statements to code accurate and deterministic hardware models, using fewer lines of
code compared to standard Verilog.

Chapter 8 provides guidelines on how to use enumerated types and specialized procedural
blocks for modeling Finite State Machine (FSM) designs. This chapter also
presents a number of guidelines on modeling hardware using 2-state logic.

Chapter 9 examines the enhancements to design hierarchy that SystemVerilog provides.
Significant constructs are presented, including nested module declarations and
simplified module instance declarations.

Chapter 10 discusses the powerful interface construct that SystemVerilog adds to
Verilog. Interfaces greatly simplify the representation of complex busses and enable
the creation of more intelligent, easier to use IP (intellectual property) models.
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Chapter 11 ties together the concepts from all the previous chapters by applying
them to a much more extensive example. The example shows a complete model of an
ATM switch design, modeled in SystemVerilog.

Chapter 12 provides another complete example of using SystemVerilog. This chapter
covers the usage of SystemVerilog to represent models at a much higher level of
abstraction, using transactions.

Appendix A lists the formal syntax of SystemVerilog using the Backus-Naur Form
(BNF). The SystemVerilog BNF includes the full Verilog-2005 BNF, with the SystemVerilog
extensions integrated into the BNF.

Appendix B lists the set of reserved keywords in the Verilog and SystemVerilog standards.
The appendix also shows how to mix Verilog models and SystemVerilog models
in the same design, and maintain compatibility between the different keyword
lists.

Appendix C presents an informative history of hardware description languages and
Verilog. It covers the development of the SUPERLOG language, which became the
basis for much of the synthesizable modeling constructs in SystemVerilog.