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发表于 2009-9-4 15:04:12
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I faced similar situation several days ago.
One simple way to solve this problem(step by step) is as follows:
Step1: Compile Xilinx Libraries,the lib source path is $ISE11.2/verilog/src/unisims/*.v($ISE11.2 is install path)
After compiled by modelsim,lib folders will be generated.
Typically,the lib names are $USER_PATH/unisims,where $USER_PATH stands for the target lib path
you defined.If you are a modelsimSE60-GUI user,$USER_PATH may be C:\Modeltech_6.0\examples.
Step2: Include compiled Xilinx Libs
example commands:
vlog -L $USER_PATH/unisims/ ...
vsim -L $USER_PATH/unisims/ ...
run -all
Step3: You should debug your design if there exists variable errors or warnnings. |
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