异步时钟域信号传输设计技术

spark.zhao

在ASIC设计中，往往会有多个异步时钟域，它们之间的数据传递和应答的时序无法使用STA工具验证，其健壮性和安全性主要依赖设计人员在设计中对异步逻辑的周密考虑。附件文中简介明了而且详细的分析了多种异步逻辑结构，并且给出了设计指导方案，可以说是一篇难得的好文，与大家共享。

Synthesis and Scripting Techniques for Designing Multi-
Asynchronous Clock Designs

Clifford E. Cummings

Sunburst Design, Inc.

ABSTRACT
Designing a pure, one-clock synchronous design is a luxury that few ASIC designers will ever
know. Most of the ASICs that are ever designed are driven by multiple asynchronous clocks and
require special data, control-signal and verification handling to insure the timely completion of a
robust working design.

MTSJNT

Thanks.

ayamitek

Thanks for sharing .........

niulinux

不错，支持一下

niulinux

不错，支持一下

spark.zhao

好东西就要顶

nzh4615

谢谢LZ的分享～

六月的乞丐

跨时钟域的的资料哈

spark.zhao

数字异步设计的经典介绍

neptune1983

跨时钟域的的资料哈