Synchronization and Arbitration in Digital Systems Wiley 2007

adefan

Preface ix
List of Contributors xiii
Acknowledgements xv
1 Synchronization, Arbitration and Choice 1
1.1 Introduction 1
1.2 The Problem of Choice 2
1.3 Choice in Electronics 3
1.4 Arbitration 5
1.5 Continuous and Discrete Quantities 6
1.6 Timing 7
1.7 Book Structure 9
Part I 11
2 Modelling Metastability 13
2.1 The Synchronizer 14
2.2 Latch Model 21
2.3 Failure Rates 23
2.3.1 Event Histograms and MTBF 28
2.4 Latches and Flip-fl ops 32
2.5 Clock Back Edge 35
3 Circuits 39
3.1 Latches and Metastability Filters 39
3.2 Effects of Filtering 41
vi CONTENTS
3.3 The Jamb Latch 42
3.3.1 Jamb Latch Flip-fl op 45
3.4 Low Coupling Latch 47
3.5 The Q-fl op 49
3.6 The MUTEX 50
3.7 Robust Synchronizer 52
3.8 The Tri-fl op 55
4 Noise and its Effects 59
4.1 Noise 59
4.2 Effect of Noise on a Synchronizer 62
4.3 Malicious Inputs 63
4.3.1 Synchronous Systems 63
4.3.2 Asynchronous Systems 66
5 Metastability Measurements 69
5.1 Circuit Simulation 69
5.1.1 Time Step Control 70
5.1.2 Long-term τ 71
5.1.3 Using Bisection 73
5.2 Synchronizer Flip-fl op Testing 75
5.3 Rising and Falling Edges 79
5.4 Delay-based Measurement 81
5.5 Deep Metastability 83
5.6 Back Edge Measurement 95
5.7 Measure and Select 97
5.7.1 Failure Measurement 97
5.7.2 Synchronizer Selection 98
6 Conclusions Part I 101
Part II 103
7 Synchronizers in Systems 105
7.1 Latency and Throughput 105
7.2 FIFO Synchronizer 108
7.3 Avoiding Synchronization 110
7.4 Predictive Synchronizers 113
7.5 Other Low-latency Synchronizers 115
7.5.1 Locally Delayed Latching (LDL) 115
7.5.2 Speculative Synchronization 118
CONTENTS vii
7.6 Asynchronous Communication Mechanisms (ACM) 125
7.6.1 Slot Mechanisms 128
7.6.2 Three-slot Mechanism 128
7.6.3 Four-slot Mechanism 130
7.6.4 Hardware Design and Metastability 132
7.7 Some Common Synchronizer Design Issues 133
7.7.1 Unsynchronized Paths 133
7.7.2 Moving Metastability Out of Sight 135
7.7.3 Multiple Synchronizer Flops 138
8 Networks and Interconnects 143
8.1 Communication on Chip 143
8.1.1 Comparison of Network Architectures 147
8.2 Interconnect Links 150
8.3 Serial Links 155
8.3.1 Using One Line 155
8.3.2 Using Two Lines 157
8.4 Differential Signalling 159
8.5 Parallel Links 161
8.5.1 One Hot Codes 162
8.5.2 Transition Signalling 166
8.5.3 n of m Codes 167
8.5.4 Phase Encoding 168
8.5.5 Time Encoding 175
8.6 Parallel Serial Links 180
9 Pausible and Stoppable Clocks in GALS 183
9.1 GALS Clock Generators 184
9.2 Clock Tree Delays 188
9.3 A GALS Wrapper 190
10 Conclusions Part II 193
Part III 197
11 Arbitration 199
11.1 Introduction 199
11.2 Arbiter Defi nition 200
11.3 Arbiter Applications, Resource Allocation Policies
and Common Architectures 202
viii CONTENTS
11.4 Signal Transition Graphs, Our Main Modelling
Language 205
12 Simple Two-way Arbiters 209
12.1 Basic Concepts and Conventions 209
12.1.1 Two-phase or Non-return-to-zero (NRZ)
Protocols 210
12.1.2 Four-phase or Return-to-zero (RTZ)
Protocols 211
12.2 Simple Arbitration Between Two Asynchronous
Requests 212
12.3 Sampling the Logic Level of an Asynchronous
Request 217
12.4 Summary of Two-way Arbiters 222
13 Multi-way Arbiters 225
13.1 Multi-way MUTEX Using a Mesh 226
13.2 Cascaded Tree Arbiters 227
13.3 Ring-based Arbiters 230
14 Priority Arbiters 235
14.1 Introduction 235
14.2 Priority Discipline 236
14.3 Daisy-chain Arbiter 238
14.4 Ordered Arbiter 239
14.5 Canonical Structure of Priority Arbiters 240
14.6 Static Priority Arbiter 241
14.7 Dynamic Priority Arbiter 246
15 Conclusions Part III 253
References 255
Index


Preface
Most books on digital design only briefl y touch on the design of
synchronizers and arbiters, with maybe two or three pages in a 300
page book, or a chapter at most. This is because there was no real need
for it in the early years of computer design. Processors were largely selfcontained
and used a single clock, so interfacing the processor to slow
peripherals, or other processors was not seen as a major task. The fact
that it is not simple emerged in the 1970s and 1980s when data rates
between processors increased, and sometimes systems with more than
one time zone were being designed. Despite frequent synchronization
failures because of lack of understanding of the design principles at
that time, synchronization still did not make it into the standard literature,
and very little has been written since about how they should be
designed. More recently processors are being designed with many more
high-speed ports linked to networks, and the systems themselves are
often made up of several core processors connected to an internal bus
or network on chip. This means that processors operating on different
time frames must communicate at high data rates, and when two or
more processors request access to a common resource, there has to be
some arbitration to decide which request to deal with fi rst.
The need for synchronizers to ensure that data coming from ...

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