Mentor Graphics Hyperlinx SI-PI v8.0 with crack

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HyperLynx 8.0新特性介绍

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HyperLynx 8.0
This latest release of HyperLynx is the most comprehensive update in the history of the
product. The most significant update is the addition of HyperLynx PI, the new Power
Integrity analysis tool. Other additions include wizards to aid in rapid setup and execution
of analysis parameters. Also, integration with Expedition Enterprise and Board Station
XE has been enhanced, making transition from schematic environment to analysis
environment much quicker and easier. Details of these, and all additions and
enhancements, are in the following sections.

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HyperLynx PI
HyperLynx PI is a significant new tool that provides the fastest time to accurate results.
Present demands on PCB design often require several — sometimes tens — of different
voltages on the same board. This means broken-up power planes that can create current
density hot spots or increased voltage drop across the plane. Beyond that, the magnitude
of the voltages (1.2 vdc or less) means that noise margins are very small. Thus, ensuring
the integrity of board power is no longer possible using the old “rules of thumb.”

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Setup Wizards
Because of the complexities of PI analysis, HyperLynx PI introduces an easy-to-use
wizard environment from which to setup and run analysis suites. The image below
illustrates the ease of stepping through the wizards to provide the necessary analysis
output. This new wizard can cut test setup from hours or days, to just a few minutes.

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Pre- and Post-Layout Analysis
The further down the design path a project moves before discovering errors, the greater
the cost to correct the error. Moving analysis as far towards the beginning of the project
as possible results in significant cost savings. HyperLynx PI allows both pre-layout and
post-layout analysis.

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Pre-Layout Analysis
Analysis with HyperLynx PI can begin prior to starting the actual layout. The Pre-layout
editor allows physical PI scenarios to be entered and simulated. For example, in the
illustration a board outline with both a split and a void is proposed. The analysis can
proceed, identifying problems and accurately determining the true number of decoupling
capacitors required for the given power and speed requirements of the PCB.

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All power integrity features are available for pre-layout use in addition to post-layout.
This allows for detailed analysis very early in the design cycle and maximum “what if?”
flexibility. For example, below, the vias proposed in the schematic are analyzed prior to
layout to determine their effects on the board’s power system.

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Post-Layout Analysis
Once the layout has been finished, a completed power integrity analysis can be run prior
to producing a prototype. Any issues can be corrected prior to spending any money on a
first product.

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Power Distribution Network Noise Analysis
Locating and rectifying noise sources affecting the power distribution network (PDN) can
be very difficult. HyperLynx PI greatly simplifies the task and provides pin-point
identification of trouble spots that need attention.
Simulation uses current pulses to imitate the I/O, core, and block power-up/down current
demand. The analysis includes effects of planes, decoupling capacitors, and stitching
vias. The results are presented graphically as a detailed noise profile, shown below.

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DC Voltage Drop Analysis
With the continued use of very low DC voltages for some applications, the DC voltage
drop along traces or voltage planes becomes critical. No longer can even 100 mV of drop
be tolerated on low voltage nets.
Fragmented or discontinuous power planes can produce excessive DC currents in
“bottlenecks.” In addition, the density of the metal, large pin fields, and vias can cause
current density issues.
Simple VRM and DC-load models are used to calculate the current density. The results
are displayed graphically so that hot-spots can be easily located and corrected, as
illustrated below.