A CMOS design of a 12-bit DAC for the AMI C5N process. Simulation results show the design can
operates on a 4MHz clock and can produce a 1.6Vpp output sine wave up to 2MHz centered at 2.2V. The
chip is a dual packaged DAC, with isolated opamp and resistor segment (for testing purposes). The DAC
accepts a 0-5V 12-bit digital input signal in binary format. The DAC topology is a Wide-Swing Current-
Mode Segmented R-2R with a R=40k
. The design has a maximum capacitive load of 50pF in parallel
with a minimum resistive load of 500
. Spectral analysis of the simulation output shows the fundamental
signal strength of a 250KHz signal to be approximately 70dB higher than the nearest overtone.
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发表于 2009-4-24 09:53:31
