【求助】Cadence IC610 在 Ubuntu8.1 license设立的问题 如何解决FLEXnet

eehigh

那位大虾能帮忙看一下，该如何解决FLEXnet的问题。
我试图把Cadence IC610 建在 Ubuntu8.1上，安装得挺顺的，license 有点问题，会碰到cds.

16:36:26 (lmgrd) Started cdslmd (internet tcp_port 52524 pid 7825)

16:36:26 (cdslmd) FLEXnet Licensing version v10.8.0.7 build 26147

16:36:27 (cdslmd) Invalid license key (inconsistent authentication code)

16:36:27 (cdslmd)
==>FEATURE Cadence_3D_Design_Viewer cdslmd 16.0 31-dec-2025 uncounted \


01357D06E4AD VENDOR_STRING=Team_EFA_2006 HOSTID=ANY ck=78 \


SIGN2="0D0D EA79 E0C1 4F48 4DCF 770A E1AE F9EF 70FB FF11 B46D \


CB35 F1D2 9A45 F4A3 05E1 EB0A CEF4 8396 87BA 7B4A BA27 CED9 \


F214 BED4 2DC6 BF6A F385 8BDA C611"

16:36:27 (cdslmd) Invalid license key (inconsistent authentication code)

16:36:27 (cdslmd)
==>FEATURE Capture cdslmd 16.0 31-dec-2025 uncounted FC5BE9761A8C \


VENDOR_STRING=Team_EFA_2006 HOSTID=ANY ck=115 SIGN2="172D DEBE \


A0EB 398F CC4A 6F83 94C4 9562 ED81 D592 F833 18A4 F5A7 009E \


EBE4 0F57 1D31 3017 21F4 CE68 9C92 4062 39AF 69FA 9B04 DEA3 \


F3BB 5CF1 2709 1BDA"

16:36:27 (cdslmd) Server started on mems for:
LayoutPlus


16:36:27 (cdslmd) Allegro_Librarian Allegro_Viewer_Plus PspiceAD


16:36:27 (cdslmd) PspiceAA
Allegro_studio
ConceptHDL


16:36:27 (cdslmd) PCB_librarian_expert SiP_Digital_Architect_GXL SiP_Digital_Architect_L

16:36:27 (cdslmd) SiP_Digital_Architect_XL SiP_Digital_Layout_GXL SiP_Digital_SI_XL

16:36:27 (cdslmd) SiP_RF_Architect_L SiP_RF_Architect_XL SiP_RF_Layout_GXL

16:36:27 (cdslmd) Allegro_Design_Editor_620 Allegro_PCB_SI_230 Allegro_PCB_SI_630

16:36:27 (cdslmd) SPECCTRAQuest_EE PCB_designer
CHDL_DesignAccess

16:36:27 (cdslmd) PE_Librarian
Checkplus_Expert Concept_HDL_rules_checker

16:36:27 (cdslmd) Concept_HDL_studio PCB_design_studio adv_package_designer_expert

16:36:27 (cdslmd) PCB_studio_variants PCB_design_expert adv_package_engineer_expert

16:36:27 (cdslmd) SPECCTRAQuest_SI_expert Concept_HDL_expert Allegro_design_expert

16:36:27 (cdslmd) advanced_package_designer Allegro_designer_suite OrCAD_PCB_Router

16:36:27 (cdslmd) OrCAD_PCB_Designer_PSpice OrCAD_PCB_Designer UNISON_SPECCTRA_6U

16:36:27 (cdslmd) SPECCTRA_Unison_Ultra SPECCTRA_Unison_PCB Unison_SPECCTRA_4U

16:36:27 (cdslmd) Allegro_PCB_Design_620 Allegro_Package_SI_620_Suite Allegro_PCB_SI_620

16:36:27 (cdslmd) Allegro_Pkg_Designer_620_Suite Allegro_PCB_Router_230 Allegro_PCB_Design_230

16:36:27 (cdslmd) Allegro_PCB_SI_630_Suite Allegro_PCB_Router_210 Allegro_PCB_Router_610

16:36:27 (cdslmd) SPECCTRA_VT
SPECCTRA_QE
SPECCTRA_performance

16:36:27 (cdslmd) SPECCTRA_PCB
SPECCTRA_HP
SPECCTRA_expert_system

16:36:27 (cdslmd) SPECCTRA_expert SPECCTRA_DFM
SPECCTRA_autoroute

16:36:27 (cdslmd) SPECCTRA_APD
SPECCTRA_ADV
SPECCTRA_6U


16:36:27 (cdslmd) SPECCTRA_256U
Allegro_performance Allegro_PCB_RF


16:36:27 (cdslmd) Allegro_PCB_Partitioning Advanced_Pkg_Engineer_3D PowerIntegrity


16:36:27 (cdslmd) SPECCTRAQuest
111
12141



16:36:27 (cdslmd) 14000
14010
14020


16:36:27 (cdslmd) 14040
14060
206


16:36:27 (cdslmd) 207
21060
21400


16:36:27 (cdslmd) 276
283
300


16:36:27 (cdslmd) 3000
3001
3011


16:36:27 (cdslmd) 302
305
311


16:36:27 (cdslmd) 3111
32100
32101


16:36:27 (cdslmd) 32120
32125
32130


16:36:27 (cdslmd) 32140
32150
32500


16:36:27 (cdslmd) 32501
32505
32510


16:36:27 (cdslmd) 32520
32521
32530


16:36:27 (cdslmd) 32760
33015
33016


16:36:27 (cdslmd) 33301
33500
33580


16:36:27 (cdslmd) 34500
34510
34511


16:36:27 (cdslmd) 34530
34570
34580


16:36:27 (cdslmd) 365
370
37100


16:36:27 (cdslmd) 374
38500
38520


16:36:27 (cdslmd) 4000
501
5100


16:36:27 (cdslmd) 550
570
681


16:36:27 (cdslmd) 70000
70110
70120


16:36:27 (cdslmd) 70130
70510
70520


16:36:27 (cdslmd) 71110
71120
71130


16:36:27 (cdslmd) 71510
71520
73510


16:36:27 (cdslmd) 73520
900
90001


16:36:27 (cdslmd) 940
945
95100


16:36:27 (cdslmd) 95115
95120
952


16:36:27 (cdslmd) 95200
95210
95220


16:36:27 (cdslmd) 95255
95300
95310


16:36:27 (cdslmd) 95320
95400
972


16:36:27 (cdslmd) 974
plotVersa
LEAPFROG-CV


16:36:27 (cdslmd) _21900
Datapath_Preview_Option Virtuoso_Turbo


16:36:27 (cdslmd) Virtuoso_XL
Encounter_C
Virtuoso_Digital_Implement

16:36:27 (cdslmd) Virtuoso_XL_Basic Virtuoso_Schem_Option Virtuoso_Turbo_Basic

16:36:27 (cdslmd) OASIS_Simulation_Interface OASIS_RFDE
Artist_Optimizer

16:36:27 (cdslmd) Artist_Statistics Corners_Analysis Affirma_3rdParty_Sim_Interface

16:36:27 (cdslmd) Affirma_RF_IC_package_modeler SpectreRF
Substrate_Coupling_Analysis

16:36:27 (cdslmd) Affirma_RF_SPW_model_link Virtuoso_Core_Optimizer Virtuoso_Core_Characterizer

16:36:27 (cdslmd) ULTRASIM
RELXPERT
UET


16:36:27 (cdslmd) Affirma_AMS_distrib_processing ADE_VoltageStorm_Option ADE_ElectronStorm_Option

16:36:27 (cdslmd) LAS_Cell_Optimization Virtuoso_Spectre Virtuoso_Spectre_RF

16:36:27 (cdslmd) virtuoso_chip_editor Virtuoso_Layout_Migrate ConcICe_Option


16:36:27 (cdslmd) AMS_environment DRAC2CORE
DRAC3CORE


16:36:27 (cdslmd) DRAC3DRC
DRACDIST
DRACERC


16:36:27 (cdslmd) Distributed_Dracula_Option DRAC3LVS
DRACLPE


16:36:27 (cdslmd) DRACPRE
DRACLVS
Assura_RCX-PL


16:36:27 (cdslmd) Assura_RCX-FS
Assura_RCX-MP
Assura_RCX-HF


16:36:27 (cdslmd) Assura_DRC
Assura_LVS
Assura_MP


16:36:27 (cdslmd) Assura_OPC
Assura_RCX
Assura_SI-TL


16:36:27 (cdslmd) Assura_SI
Assura_SiMC
Assura_SiVL


16:36:27 (cdslmd) Assura_UI
Assura_DV_design_rule_checker Assura_DV_parasitic_extractor

16:36:27 (cdslmd) Assura_DV_LVS_checker Physical_Verification_Sys_L Physical_Verification_Sys_XL

16:36:27 (cdslmd) skillDev
Affirma_sim_analysis_env Virtuoso_Multi_mode_Simulation

16:36:27 (cdslmd) Virtuoso_Schematic_Editor_L Virtuoso_Schematic_Editor_XL Virtuoso_Schematic_Editor_GXL

16:36:27 (cdslmd) Composer_EDIF300_Connectivity Analog_Design_Environment_L Analog_Design_Environment_XL

16:36:27 (cdslmd) Analog_Design_Environment_GXL Virtuoso_Visual_Analysis_XL Composer_EDIF300_Schematic

16:36:27 (cdslmd) Virtuoso_Layout_Suite_L Virtuoso_Layout_Suite_XL Virtuoso_Layout_Suite_GXL

16:36:27 (cdslmd) Virtuoso_Constraint_API Spectre_BTAHVMOS_Models Spectre_BTASOI_Models

16:36:27 (cdslmd) tw01
tw02


16:36:27 (cdslmd)

16:36:27 (cdslmd) All FEATURE lines for cdslmd behave like INCREMENT lines

16:36:27 (cdslmd)

16:36:27 (lmgrd) cdslmd using TCP-port 52524

16:36:27 (cdslmd) Can't make directory /usr/tmp/.flexlm, errno: 2(No such file or directory)

16:37:27 (cdslmd) Can't make directory /usr/tmp/.flexlm, errno: 2(No such file or directory)

16:38:27 (cdslmd) Can't make directory /usr/tmp/.flexlm, errno: 2(No such file or directory)

16:39:27 (cdslmd) Can't make directory /usr/tmp/.flexlm, errno: 2(No such file or directory)

16:40:27 (cdslmd) Can't make directory /usr/tmp/.flexlm, errno: 2(No such file or directory)

zxc6

是不是没有权限啊

jcz_100

我也有同样的问题！！

lwm2kj

我也有同样的问题！请高手帮助

filetemp

I don't know much, but i know reason of the following lines:
16:40:27 (cdslmd) Can't make directory /usr/tmp/.flexlm, errno: 2(No such file or directory)
1.
The lmgrd run by non-root user.
2.
before , lmgrd run by root
and /usr/tmp/.flexlm is a directory and create by root
and the non-root can't have write access.
3.
so run the following by root :
chown  -R xxx:xxx  /usr/tmp/.flexlm
(xxx is you non-root username that you want to run lmgrd )

4. the following line:
(cdslmd) Invalid license key (inconsistent authentication code)
I guess , but not make sure , the reason is :
you don't have the ECC patch to your cdslmd

zq496547199

帮顶，有没有高人帮忙

M34791496

什么是ECC Patch?如果是6楼说的那个原因，那solution是什么?

dreamfly123123

谢谢楼主

usleesa

thanks~