Model order reduction method for interconnect modeling in IC design

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Model order reduction method for interconnect modeling in IC design

Due to the recent advances in silicon technologies, interconnect modeling and simulation have become important concerns in high performance circuit design. Because of the size of the interconnect networks, model order reduction methods are needed to do fast and efficient interconnect modeling and simulation. In this dissertation, we present the passive model order reduction methods which reduce the order of the original interconnect network to a much smaller one. And by these new methods it is possible to do the signal integrity verification which helps improve the interconnect delay, crosstalk risk of the chip, voltage drops and ground bounces.;In the first part of this thesis, the passive model order reduction methods are investigated. The goal is to improve the chip performance by analyzing the interconnect networks. Since the size of the interconnect networks is usually extremely huge, we develop a new multipoint multiport model order reduction method for lumped RLC interconnect networks which allows the fast simulation of the huge size interconnect networks. For the modeling and simulation of transmission lines, we design a L2[0,1] Hilbert space theory based model order reduction approach which performs the passive reduction for distributed lines. Both of these methods are based on the multipoint moment matching. Experience has shown that single point moment matching approaches are not as accurate as multipoint ones. However, it is not easy to estimate the expansion points. In order to overcome this difficulty, Chebyshev expansion based method is also discussed in this thesis. Experiments show that these approaches can achieve good speedup over SPICE while obtain the same accuracy.;In the second part of this thesis, Signal Integrity Verification (SIV) is discussed. The aim is to avoid the signal integrity violation at 0.25μ m feature size and below. Examples of signal integrity violation are: (1) false switching due to glitches; (2) deterioration in timing performance due to long/short, setup/hold and delay times; (3) current density and electromigration in signal lines; (4) IR drop in power grids. All these problems are discussed in this thesis. And our passive model order reduction approaches can be used as the core part of Signal Integrity Verification (SIV).

bing131

下来看看什么好书

skrainbow

怎么下不了？

skrainbow

kankan

smithwood99

good stuff

hezudao

ding ding a

feiwang

greattttttttttttttttttttttt

feiwang

thankx

chupws

值得看看，谢谢楼主分享……

chupws

谢谢楼主分享，本人正在学习中哦……