there are three kinds of major leakage currents in advanced CMOS processes:  (a)   tunneling leakage, which relates to the gate   
oxide thickness;
(b) subthreshold leakage
(c) junction diode leakage, which relates to the parasitic pn junctions.
the cross-coupled pair enlarges the output swing in delay cell of vco.
Yes, that is why you have to pay attention when designing such a Loop filter in deep-sub micro process. Many design techniques fail and have to modify for it to work under high leakage conditions.