Springer Analog circuits and signal processing serials (总共36本, 搜集了30本)

tjumicrosoft

只见回复无人下载啊

handchief581

第十本
Broadband Opto-Electrical Receivers in Standard CMOS

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Broadband Opto-Electrical Receivers in Standard CMOSSeries: Analog Circuits and Signal Processing Hermans, Carolien, Steyaert, Michiel 2007, 250 p., Hardcover

About this book
Broadband Opto-Electrical Receivers in Standard CMOS fits in the quest for integrated opto-electrical solutions, and focuses on the receiver front-end. To further reduce the cost, the cheapest technology is selected: standard CMOS, without any optical tricks or flavors. The emphasis is on the analysis, design and implementation of high-performance analog receiver circuits.
Broadband Opto-Electrical Receivers in Standard CMOS starts from the basic fundamentals, necessary for the design of opto-electronic interface circuits. The book continues with an in-depth analysis of the photodiode, transimpedance amplifier (TIA) and limiting amplifier (LA). To thoroughly understand the light detection mechanisms in silicon, first a one-dimensional and second a two-dimensional model is developed. Analytical design equations are derived to guide the design of the amplifying circuits. For the TIA, the focus lies on the sensitivity-speed trade-off. For the LA, a high gain-bandwidth is pursued. Several practical design examples reveal the subtleties and challenges encountered during the design of high-performance analog circuits.
Broadband Opto-Electrical Receivers in Standard CMOS covers the total design flow of monolithic CMOS optical receivers. All material is experimentally verified with several CMOS implementations, with ultimately a fully integrated Gbit/s optical receiver front-end including photodiode, TIA and LA. The book is essential reading for analog design engineers and researchers in the field and is also suitable as a text book for an advanced course on the subject.

Written for:
Scientists, master and Ph.D. students, analog design engineers, researchers in the field

handchief581

第十一本
Circuit and Interconnect Design for RF and High Bit-Rate Applications

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Circuit and Interconnect Design for RF and High Bit-rate ApplicationsSeries: Analog Circuits and Signal Processing Veenstra, Hugo, Long, John R. 2008, XII, 248 p., Hardcover ISBN: 978-1-4020-6882-9

About this book
Realizing maximum performance from high bit-rate and RF circuits requires close attention to IC technology, circuit-to-circuit interconnections (i.e., the ‘interconnect’) and circuit design. Circuit and Interconnect Design for RF and High Bit-rate Applications covers each of these topics from theory to practice, with sufficient detail to help you produce circuits that are ‘first-time right’. A thorough analysis of the interplay between on-chip circuits and interconnects is presented, including practical examples in high bit-rate and RF applications. Optimum interconnect geometries for the distribution of RF signals are described, together with simple models for standard interconnect geometries that capture characteristic impedance and propagation delay across a broad frequency range. The analyses also cover single-ended and differential geometries, so that the designer can incorporate the effects of interconnections as soon as estimated interconnect lengths are available. Application of interconnect design is illustrated using a 12.5 Gb/s crosspoint switch example taken from a volume production part.
From the technology perspective, transistor performance and its relationship to design targets for high bit-rate and RF applications is extensively discussed. Traditional figures of merit, such as fT and fmax and their relevance to circuit design are discussed, and new figures of merit are introduced that are shown to be highly valuable for broadband circuit and oscillator design. In addition, an analysis of transistor operation at supply voltages above breakdown voltage BVCEO, is presented.

Written for:
Electronic engineers, involved in circuit design for high bit-rate and/or RF applications

handchief581

第十二本
CMOS Cascade Sigma-Delta Modulators for Sensors and Telecom

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CMOS Cascade Sigma-Delta Modulators for Sensors and TelecomError Analysis and Practical Design Series: Analog Circuits and Signal Processing Río, R.d., Medeiro, F., Pérez-Verdú, B., de la Rosa, J.M., Rodríguez-Vázquez, Á. 2006, XXI, 299 p., Hardcover ISBN: 978-1-4020-4775-6

About this book
CMOS Cascade Sigma-Delta Modulators for Sensors and Telecom: Error Analysis and Practical Design presents architectures, circuits, models, methods and practical considerations for the design of high-performance low-pass switched-capacitor (SC) sigma-delta A/D interfaces for mixed-signal CMOS ASICs. Main focus is on cascade architectures, although considerations pertaining to circuits and error analysis are general and hence valid for other architectures.
The book differs from others in the complete, in-depth coverage of SC circuit errors, in the detailed elaboration and description of practical design plan, and in the thorough presentation of considerations leading to practical high-performance designs. Another differentiating feature of this book is the coverage into a unified description of largely different application areas. On the one hand, sensor front-ends, where the limiting factor is thermal noise. On the other, wire-line telecom front-ends, where the limiting factor is linked to the dynamic behavior of the building blocks.
The book starts with a tutorial presentation of the fundamentals of low-pass sigma-delta modulators, their applications, and their most common architectures. This presentation is both complete and comprehensive. It then presents an exhaustive analysis of SC circuit errors with a twofold outcome. On the one hand, compact expressions are derived to support design plans and quick top-down design. On the other, detailed behavioral models are presented to support accurate verification. This set of models allow the designer to determine the required specifications for the different modulator building blocks and form the basis of a systematic design approach. The book is completed in subsequent chapters with the detailed presentation of three high-performance modulator ICs: the first two are intended for DSL-like applications, whereas the third one is intended for automotive sensors.
CMOS Cascade Sigma-Delta Modulators for Sensors and Telecom: Error Analysis and Practical Design contains highly valuable information that is structured to give the reader the necessary insight on how to design SC sigma-delta modulators. In this sense, the book is intended for a large audience: from mixed-signal designers who want to optimize and to shorten the design cycle of sigma-delta modulators with challenging specifications, to non-experienced readers who want a comprehensive and practical description of sigma-delta design and SC errors.

Written for:
Mixed-signal designers, non-experienced graduate students in the field of Microelectronics, can also be used in undergraduate courses

handchief581

第十三本
CMOS Current-Mode Circuits for Data Communications

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CMOS Current-Mode Circuits for Data CommunicationsSeries: Analog Circuits and Signal Processing Yuan, Fei 2007, XVIII, 290 p., Hardcover

About this book
This book deals with the analysis and design of CMOS current-mode circuits for data communications. CMOS current-mode sampled-data networks, i.e. switched-current circuits, are excluded. Major subjects covered in the book include: a critical comparison of voltage-mode and current-mode circuits; the building blocks of current-mode circuits: design techniques; modeling of wire channels, electrical signaling for Gbps data communications; ESD protection for current-mode circuits and more. This book will appeal to IC design engineers, hardware system engineers and others.

Written for:
Integrated circuits design engineers, hardware system engineers

benemale

CMOS Multichannel Single-Chip Receivers for Multi-Gigabit Optical Data Communications

这本书在你提到的我的帖子里有.

handchief581

第十四本
CMOS Multichannel Single-Chip Receivers for Multi-Gigabit Optical Data Communications

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CMOS Multichannel Single-Chip Receivers for Multi-Gigabit Optical Data CommunicationsSeries: Analog Circuits and Signal Processing Muller, Paul, Leblebici, Yusuf 2007, XX, 192 p., Hardcover ISBN: 978-1-4020-5911-7

About this book
While the throughput of microprocessor systems tends to increase as a result of ongoing technology scaling and the advent of multi-core systems, the off-chip I/O communication bandwidth emerges as one of the potential bottlenecks that limit overall performance. In order to alleviate the communication speed constraints, optical data communication interfaces move ever closer to the processor core. It is widely expected that future generation digital systems will increasingly rely on chip-to-chip and board-to-board optical data communications for higher bandwidth and better noise immunity.
This book focuses on optical communications for short and very short distance applications and discusses the monolithic integration of optical receivers with processing elements in standard CMOS technologies. CMOS Multi-Channel Single-Chip Receivers for Multi-Gigabit Optical Data Communications provides the reader with the necessary background knowledge to fully understand the trade-offs in short-distance communication receiver design and presents the key issues to be addressed in the development of such receivers in CMOS technologies. Moreover, novel design approaches are presented. A system-level design methodology allows for the impact analysis of different block specifications and system-wide design optimization. Statistical models are used for design space exploration in the scope of jitter tolerance analysis of clock recovery circuits.
CMOS Multi-Channel Single-Chip Receivers for Multi-Gigabit Optical Data Communications is required reading for practicing engineers and researchers in the field of short-distance optical communications and optical CMOS receiver design.

Written for:
Researchers and circuit designers in the field of CMOS optical communications, Electrical and Electronics Engineering Graduate students

handchief581

第十五本
CMOS Single Chip Fast Frequency Hopping Synthesizers for Wireless Multi-Gigahertz Applications

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CMOS Single Chip Fast Frequency Hopping Synthesizers for Wireless Multi-Gigahertz ApplicationsDesign Methodology, Analysis, and Implementation Series: Analog Circuits and Signal Processing Bourdi, Taoufik, Kale, Izzet 2007, XII, 208 p., Hardcover ISBN: 978-1-4020-5927-8

About this book
Recently, wireless LAN standards have emerged in the market. Those standards operate in various frequency ranges. To reduce component count, it is of importance to design a multi-mode frequency synthesizer that serves all wireless LAN standards including 802.11a, 802.11b and 802.11g standards. With different specifications for those standards, designing integer-based phase-locked loop frequency synthesizers can not be achieved. Fractional-N frequency synthesizers offer the solution required for a common multi-mode local oscillator. Those fractional-N synthesizers are based on delta-sigma modulators which in combination with a divider yield the fractional division required for the desired frequency of interest.
In CMOS Single Chip Fast Frequency Hopping Synthesizers for Wireless Multi-Gigahertz Applications, the authors outline detailed design methodology for fast frequency hopping synthesizers for RF and wireless communications applications. Great emphasis on fractional-N delta-sigma based phase locked loops from specifications, system analysis and architecture planning to circuit design and silicon implementation.
The book describes an efficient design and characterization methodology that has been developed to study loop trade-offs in both open and close loop modelling techniques. This is based on a simulation platform that incorporates both behavioral models and measured/simulated sub-blocks of the chosen frequency synthesizer. The platform predicts accurately the phase noise, spurious and switching performance of the final design. Therefore excellent phase noise and spurious performance can be achieved while meeting all the specified requirements. The design methodology reduces the need for silicon re-spin enabling circuit designers to directly meet cost, performance and schedule milestones.
The developed knowledge and techniques have been used in the successful design and implementation of two high speed multi-mode fractional-N frequency synthesizers for the IEEE 801.11a/b/g standards. Both synthesizer designs are described in details.

Written for:
RFIC, RF, wireless IC and system design engineers and academics involved in the teaching, research, design and/or implementation of high purity and fast switching speed frequency synthesizers for various wireless applications and standards such as GSM, WLAN and WIMAX

[ 本帖最后由 handchief581 于 2009-2-26 18:31 编辑 ]

handchief581

第十六本
Design of High Voltage xDSL Line Drivers in Standard CMOS

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Design of High Voltage xDSL Line Drivers in Standard CMOSSeries: Analog Circuits and Signal Processing Serneels, Bert, Steyaert, Michiel 2008, XIV, 186 p., Hardcover ISBN: 978-1-4020-6789-1

About this book
Design of high voltage xDSL line drivers in standard CMOS fits in the quest for highly efficient fully integrated xDSL modems for central office applications. The book focusses on the line driver, the most demanding building block of the xDSL modem for lowering power. To reduce the cost, the cheapest technology is selected: standard CMOS, without any extra process options to increase the nominal supply voltage. The emphasis lies on the analysis, design and implementation of high voltage highly efficient line drivers in mainstream CMOS.

Design of high voltage xDSL line drivers in standard CMOS starts from the Self-Oscillating Power Amplifier (SOPA), a highly efficient line driver for xDSL applications. However, in the nano-electronic era, the low supply voltage of CMOS results in very low efficiencies for line drivers and power amplifiers in general. In this book a technique is developed for designing high voltage circuits in a low voltage mainstream CMOS technology. Several practical design examples reveal the subtleties and challenges encountered during the design of high voltage circuits in low voltage standard CMOS. Such a high voltage buffer is then integrated into the SOPA architecture leading to the implementation of a high voltage highly efficient aDSL2+ line driver in a 1.2V 130nm mainstream CMOS technology.

Design of high voltage xDSL line drivers in standard CMOS covers the total design flow of monolithic CMOS high voltage circuits. The book is essential reading for analog design engineers and researchers in the field and is also suitable as a text book for an advanced course on the subject.

Written for:
Graduate level students, researchers and professionals in the area of Analog Circuit Design, RF and Communications

handchief581

第十七本
Full-Chip Nanometer Routing Techniques

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Full-Chip Nanometer Routing TechniquesSeries: Analog Circuits and Signal Processing Ho, Tsung-Yi, Chang, Yao-Wen, Chen, Sao-Jie 2007, XIV, 102 p., Hardcover ISBN: 978-1-4020-6194-3

About this book
As Moore's Law continues unencumbered into the nanometer era, chips are reaching 1000 M gates in size, process geometries have shrunk to 90 nm and below, and engineers have to face compounded design complexity with every new design. These nanometer-scale designs require a new generation of physics-aware and manufacturing-aware routing. At 90 nm and below, there are so many signal-integrity issues that design teams cannot manually correct them all. At 90 nm, wires account for nearly 75% of the total delay in a circuit. Even more insidious, however, is that among nearly 40% of these nets, more than 50% of their total net capacitance are attributed to the cross-coupling capacitance between neighboring signals. At this point a new design and optimization paradigm based on real wires is required. Nanometer routers must prevent and correct these effects on-the-fly in order to reach timing closure. From a manufacturability standpoint, nanometer routers must explicitly deal with the ever increasing design complexity, and be capable of adapting to the constraint requirements of timing, signal integrity, process antenna effect, and new interconnect architecture such as X-architecture.
In the nanometer era, we must look into new-generation routing technologies that combine high performance and capacity with the integration of congestion, timing, SI prevention, and DFM algorithms as the best means of getting to design closure quickly. In this book, we present a novel multilevel full-chip router, namely mSIGMA for SIGnal-integrity and MAnufacturability optimization. And these routing technologies will ensure faster time-to-market and time-to-profitability.

Written for:
Graduate level students and professionals in the area of physical design, Computer-Aided Design, VLSI design and digital design