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楼主: linquln

国外运放博士论文Design of an integrated full differential operational amplifier

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发表于 2009-2-9 10:02:20 | 显示全部楼层
gooooooooooooooood!!!!!!!!!!!!!!!!!!!!!!!!
发表于 2009-2-16 01:40:18 | 显示全部楼层
duo xie a
发表于 2009-2-16 01:42:12 | 显示全部楼层
liang ge you shenme qubie?
 楼主| 发表于 2009-2-17 09:36:24 | 显示全部楼层
两篇论文的题目和摘要补发如下:
Design of an integrated full differential operational amplifier
Abstract:
This paper explains the choice made for a full differential operational amplifier. This op amp has
been designed for the first stage of a pipelined A/D Converter (ADC). This means that it has the
highest specification of every op amp of all stages, as it concerns the LSB of the ADC. It shows
also the solution founded to reach high gain and short settling time, without degrading too much
the output swing.
First the operational amplifier specification are explained; the different structures tested are then
presented and the motivation of the final topology choice are shown. It presents then the op amp
schematic implementation, the simulation results and the layout with the 0.35um CMOS-AMS
design kit.
NO2-gmID-Improvements in biasing, compensation and design methods of CMOS operational amplifiers
Abstract:
This thesis presents a design methodology for CMOS integrated circuits based on the MOSFET gate-transconductance-to-drain-current ratio (gm/I D), and the Advanced Compact MOSFET (ACM) model. The design methodology is more suited to current challenges in analog design than existing methodologies because it allows designers to work in weak, moderate, and strong inversion. Using the design methodology, I show how common circuit specifications can be related to gm/ID of MOSFETs within the opamp.;Additionally, I present modifications to constant-gm biasing and Miller-lead compensation that mitigate some of their shortcomings. I describe a new constant-gm bias circuit with improved stability. I also present a lead compensation technique with improved stability over load variations.;To demonstrate the circuits and the design methodology, I fabricated a test chip in 0.8mum BiCMOS. Simulation results are presented showing a 75% reduction in compensation capacitance for the constant-gm bias circuit, and a 40° improvement in opamp phase margin.
发表于 2009-3-8 12:09:12 | 显示全部楼层

eetop

:victory: :victory:
发表于 2009-3-9 22:20:59 | 显示全部楼层
haodongx
发表于 2009-3-10 21:55:20 | 显示全部楼层
kankan
发表于 2009-3-17 18:45:03 | 显示全部楼层
thanks
发表于 2009-3-17 20:07:15 | 显示全部楼层
谢谢楼主
发表于 2009-3-17 20:08:20 | 显示全部楼层
谢谢。。。。
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