ESD：柯明道08年的几篇ESD文章

flyfeng

附件是柯教授08年的文章，对ESD有兴趣的可以看看

flyfeng

上面文章的摘要：
Abstract-Low capacitance (low-C) design on ESD protection device
is a solution to mitigate the radio-frequency (RF) performance
degradation caused by electrostatic discharge (ESD) protection
device. Silicon-controlled rectifier (SCR) device has been used as
an effective on-chip ESD protection device in RF ICs due to the
smaller layout area and small parasitic capacitance under the
same ESD robustness. In this paper, the modified lateral SCR
(MLSCR) realized in waffle layout structure is studied to minimize
the parasitic capacitance and the variation of the parasitic
capacitance within ultra-wide band (UWB) frequencies. With the
minimized parasitic capacitance, the degradation on RF circuit
performance due to ESD protection devices can be reduced. The
waffle MLSCR with low parasitic capacitance is suitable for
on-chip ESD protection in UWB RF ICs. Besides, the turn-on
speed of MLSCR with waffle layout structure is verified to be
better than that with conventional stripe structure.

flyfeng

第二篇：
摘要：ABSTRACT
A new on-chip transient detection circuit for system-level
electrostatic discharge (ESD) protection is proposed. By including
this new proposed on-chip transient detection circuit, a
hardware/firmware solution cooperated with power-on reset circuit
can be co-designed to fix the system-level ESD issues. The circuit
performance to detect different positive and negative ESD-induced
fast electrical transients has been investigated by HSPICE simulator
and verified in silicon chip. The experimental results in a 0.18-􀁐m
CMOS process have confirmed that the proposed on-chip transient
detection circuit can detect fast electrical transients during systemlevel
ESD zapping.

flyfeng

第三篇：
ABSTRACT
To mitigate the radio-frequency (RF) performance degradation caused by
electrostatic discharge (ESD) protection device, low capacitance (low-C)
design on ESD protection device is a solution. With the smaller layout
area and small parasitic capacitance under the same ESD robustness,
silicon-controlled rectifier (SCR) device has been used as an effective
on-chip ESD protection device in RF ICs. In this paper, the modified
lateral SCR (MLSCR) with the waffle layout structure is studied to
minimize the parasitic capacitance and the variation of the parasitic
capacitance within ultra-wide band (UWB) frequencies. With the
minimized parasitic capacitance, the degradation on RF circuit
performance can be reduced. Besides, the fast turn-on design on MLSCR
without extra parasitic capacitance from the trigger circuit adding on the
I/O pad is also investigated in this work.

flyfeng

第四篇：
ABSTRACT
The electrostatic discharge (ESD) protection
design for high-speed input/output (I/O) interfaces
in a 130-nm CMOS process is proposed in this
paper. First, the ESD protection devices were
designed and fabricated to evaluate their ESD
robustness and the parasitic effects in giga-hertz
frequency band. With the knowledge on the
dependence of device dimensions on ESD
robustness and the parasitic capacitance, the ESD
protection circuit for high-speed I/O interfaces was
designed with minimum degradation on high-speed
circuit performance but satisfactory high ESD
robustness.

flyfeng

好资料自己顶

tkwin

不错的资料

liuhero_008

jessiexh

好资料，帮着顶！

killyou_6

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