【新】ADAPTIVE FILTER ARCHITECTURES FOR FPGA IMPLEMENTATION

huhaohoo

1 Introduction
1.1 Purpose.................................................................................................................. 1
1.2 Overview............................................................................................................... 1
1.2.1 Advantages of DSP..................................................................................... 2
1.2.2 Reconfigurable Hardware Advantages ................................................... 2
1.3 Organization of Thesis ........................................................................................ 3
2 Programmable Logic Devices
2.1 History of Programmable Logic ......................................................................... 4
2.2 FPGA Architecture................................................................................................ 6
2.3 Device Configuration ........................................................................................... 9
2.3.1 Schematic Design Entry .............................................................................. 9
2.3.2 Hardware Description Languages ............................................................11
2.3.3 High‐Level Languages ................................................................................11
2.4 Current Trends ......................................................................................................12
3 Adaptive Filter Overview
3.1 Introduction .......................................................................................................... 13
3.2 Adaptive Filtering Problem................................................................................ 14
3.3 Applications.......................................................................................................... 15
3.4 Adaptive Algorithms........................................................................................... 16
3.4.1 Wiener Filters............................................................................................... 17
3.4.2 Method of Steepest Descent ...................................................................... 19
3.4.3 Least Mean Square Algorithm .................................................................. 20
3.4.4 Recursive Least Squares Algorithm ......................................................... 21
4 FPGA Implementation
4.1 FPGA Realization Issues ..................................................................................... 23
4.2 Finite Precision Effects ........................................................................................ 24
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4.2.1 Scale Factor Adjustment............................................................................. 24
4.2.2 Training Algorithm Modification............................................................. 27
4.3 Loadable Coefficient Filter Taps........................................................................ 31
4.3.1 Computed Partial Products Multiplication............................................. 31
4.3.2 Embedded Multipliers ............................................................................... 34
4.3.3 Tap Implementation Results ..................................................................... 34
4.4 Embedded Microprocessor Utilization............................................................. 37
4.4.1 IBM PowerPC 405 ....................................................................................... 37
4.4.2 Embedded Development Kit..................................................................... 38
4.4.3 Xilinx Processor Soft IP .............................................................................. 38
4.4.3.1 User IP Cores ................................................................................... 39
4.4.4 Adaptive Filter IP Core .............................................................................. 41
5 Results
5.1 Methods Used....................................................................................................... 42
5.2 Algorithm Analyses............................................................................................. 44
5.2.1 Full Precision Analysis............................................................................... 44
5.2.2 Fixed‐Point Analysis................................................................................... 46
5.3 Hardware Verification......................................................................................... 48
5.4 Power Consumption............................................................................................ 49
5.5 Bandwidth Considerations................................................................................. 50
6 Conclusions
6.1 Conclusions........................................................................................................... 52
6.2 Future Work.......................................................................................................... 53
Appendix A Matlab Code........................................................................................... 55
Appendix B VHDL Code............................................................................................ 59
Appendix C C Code .................................................................................................... 75
Appendix D Device Synthesis Results ................................................................... 80
References ..................................................................................................................... 83
Biographical Sketch .................................................................................................... 86

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