发几篇博士论文，学习一下

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An Ultra-Low-Quiescent-Current Dual-Mode Digitally-Controlled Buck Converter IC for
Cellular Phone Applications

Copyright Fall 2003 by Jinwen Xiao

University of California, Berkeley

This dissertation presents a low-quiescent-current dual-mode digitally-controlled buck converter
IC for cellular phone applications. In cellular phones, the load current demanded by
the on-board circuitry varies from below 0.1 mA up to a few hundred mA, reflecting operation
in standby and active (talk) modes. Thus, high efficiency over a wide load range is of
high priority for power management units, since the total energy is limited by the capacity
of a single cell Li-ion battery. A dual-mode buck converter IC, implemented with a 0.25-
μm CMOS process, takes 2 mm2 active area and demonstrates equal or better regulation
performance compared to state-of-the-art analog switchers. A very low quiescent current of
4 μA is achieved experimentally, resulting in a more than three-fold reduction compared to
the leading state-of-the-art analog controllers. Consequently, a high efficiency, exceeding
70%, is achieved over a wide load range between 0.1 and 400 mA.

hktkzsw

Advanced Pulse Width Modulation Controller ICs for Buck DC-DC

Jianhui Zhang

UNIVERSITY OF CALIFORNIA, BERKELEY

This dissertation develops power management ICs to tackle the challenges for
both accurate and e±cient power delivery for today's high performance processors.
A double-edge multi-phase low-latency pulse width modulator IC is implemented in
0.18 ¹m CMOS process with 0.04 mm2 active area and demonstrates a fast double-
edge pulse width modulation scheme which is important for achieving fast controller
response for high bandwidth applications. A multi-mode 4-phase digital IC controller
for voltage regulator application is implemented in 0.18 ¹m CMOS process with 4
mm2 active area. The controller combines load current feedforward with voltage mode
feedback to achieve fast transient response and multi-mode control strategy improves
the converter e±ciency by at least a factor of ten in light load condition. A load-
2
scheduled integrator array is developed in the controller IC which improves the load
transient response when voltage regulator transitions between continuous conduction
mode and discontinuous conduction mode.

hktkzsw

LOW-VOLTAGE ANALOG CMOS ARCHITECTURES
AND DESIGN METHODS

Kent D. Layton

December 2007

This dissertation develops design methods and architectures which allow ana-
log circuits to operate at VT + 2Vds;sat, the minimum supply for CMOS circuits with
all transistors in the active region where Vds;sat is the drain to source saturation volt-
age of a MOS transistor. Techniques which meet this criteria for rail-to-rail input
stages, gain enhancement stages, and output stages are discussed and developed.
These techniques are used to design four fully-di®erential rail-to-rail ampli¯ers. The
highest gain is shown to be attained using a drain voltage equalization (DVE) or
active-bootstrapping technique which produces more than 100dB of gain in a two
stage ampli¯er with a bulk-driven input pair while showing no bandwidth degrada-
tion when compared to ampli¯er architectures with similar biasing. The low voltage
design techniques are extended to switching and sampling circuits. A 10-bit digi-
tal to analog converter (DAC) and a 10-bit analog to digital converter (ADC) are
designed and fabricated in a 0:35¹m dual-well CMOS process to prove the devel-
oped design methods, architectures, and techniques. The 10-bit DAC operates at
1MSPS with near rail-to-rail di®erential output operation with a 700mV supply volt-
age. This supply voltage, which is 150mV lower than the VT+2Vds;sat limit, is attained
by using a bulk driven threshold voltage lowering technique. The ADC design is a
fully-di®erential pipelined 10-bit converter that operates at 500kSPS with a full scale
input range equal to the supply voltage and can operate at supply voltages as low as
650mV, 200mV below the VT + 2Vds;sat limit. The design methods and architectures
can be used in advanced processes to maintain gain and minimize supply voltage.
These designs show a minimum supply improvement over previously published de-
signs and prove the e±cacy of the design architectures and techniques presented in
this dissertation.

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final

herrgeothe

谢谢楼主，第二篇我坚决收藏了，好资料啊。。。。

grace01

支持中

zhanweisu27

anyway


it is very good paper

myota

不错，不过google一下就可免费下载到

sdlgc

kan kan