DDR2 memory busses vary depending on the
intended market for the finished product. Some products
must support four or more registered DIMMs,
some are point-to-point topologies. This document
focuses on solutions requiring two unbuffered DIMMs
operating at a data rate of 533 megabits per second
(Mb/s). It is intended to assist board designers with the
development and implementation of their products.
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发表于 2008-10-23 17:23:27
