Ming-Dou Ker CMOS ESD DESIGN (IEEE 2008) Papers

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Ming-Dou Ker  CMOS ESD DESIGN (IEEE 2008) Papers

CMOS Power Amplifier with ESD Protection Design
Merged in Matching Network

Abstract—A power amplifier (PA) with combination of ESD
protection circuit and matching network into single block was
proposed and implemented in a 0.18-μm CMOS process. By
comprising ESD protection function into the matching network,
this design omits individual I/O ESD clamps to alleviate
loading that degrades RF performances. According to the
experimental results, the ESD protection circuit with LC
configuration contributes a 3.0-kV human body model (HBM)
ESD robustness without significant degradation on RF
performances of the PA for 2.4-GHz RF applications.

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HIGH-ROBUST ESD PROTECTION STRUCTURE WITH EMBEDDED SCR
IN HIGH-VOLTAGE CMOS PROCESS

ABSTRACT
The dependence of device structures and layout parameters on
ESD robustness of HV MOSFETs in high-voltage 40-V CMOS
process has been investigated by device simulation and verified in
silicon test chips. It was demonstrated that a new ESD protection
structure with p-type SCR embedded into the HV PMOS has the
highest ESD robustness in a given 40-V CMOS process.

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2xVDD-Tolerant Crystal Oscillator Circuit Realized
With 1xVDD CMOS Devices Without Gate-Oxide
Reliability Issue

Abstract—A new 2xVDD-tolerant crystal oscillator circuit
realized with 1xVDD CMOS devices without suffering gateoxide
reliability issue is proposed, which is one of the key mixedvoltage
I/O cells in a cell library. The proposed circuit is realized
with only thin gate-oxide devices with floating n-well technique.
The proposed 2xVDD-tolerant crystal oscillator circuit has been
designed and verified in a 90-nm 1-V CMOS process to serve
1/2-V mixed-voltage interface applications.

IV. CONCLUSION
A new proposed 2xVDD-tolerant crystal oscillator circuit
has been successfully designed and implemented in a 90-nm
1-V CMOS process, which can be operated in the 1/2-V signal
environment without the gate-oxide reliability problem. The
new mixed-voltage-tolerant crystal oscillator circuit can be
applied for external clock signal in the input pad (XI) without
the gate-oxide reliability problems. The new mixed-voltagetolerant
crystal oscillator circuit realized with 1xVDD devices
can be applied in 1xVDD/2xVDD mixed-voltage interface.

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Optimization on SCR Device With
Low Capacitance for On-Chip ESD Protection in
UWB RF Circuits

Chun-Yu Lin and Ming-Dou Ker
Nanoelectronics and Gigascale Systems Laboratory, Institute of Electronics, National Chiao-Tung University, Taiwan

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semico_ljj

CCDDCCDD

ferdinands

这个要顶你一下阿。。。

killyou_6

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killyou_6

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