Design of Very High-Frequency Multirate Switched-Capacitor Circuits

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Design of Very High-Frequency Multirate Switched-Capacitor Circuits: Extending the Boundaries of CMOS Analog Front-End Filtering (The Springer International Series in Engineering and Computer Science)
By U Seng-Pan, Rui Paulo Martins, José Epifânio da Franca
Contents
Dedication v
Preface xiii
Acknowledgment xvii
List of Abbreviations xix
List of Figures xxiii
List of Tables xxxi
1 INTRODUCTION 1
1. High-Frequency Integrated Analog Filtering...................................1
2. Multirate Switched-Capacitor Circuit Techniques...........................3
3. Sampled-Data Interpolation Techniques..........................................5
4. Research Goals and Design Challenges...........................................8
2 IMPROVEDMULTIRATE POLYPHASE-BASED INTERPOLATION
STRUCTURES 15
1. Introduction....................................................................................15
2. Conventional and Improved Analog Interpolation.........................16
3. Polyphase Structures for Optimum-class Improved Analog
Interpolation ...................................................................................20
4. Multirate ADB Polyphase Structures.............................................22
viii Design of Very High-Frequency Multirate Switched-Capacitor Circuits –
Extending the Boundaries of CMOS Analog Front-End Filtering
4.1 Canonic and Non-Canonic ADB Realizations .......................22
4.1.1 FIR System Response .................................................22
4.1.2 IIR System Response ..................................................24
4.2 SC Circuit Architectures ........................................................26
5. Low-Sensitivity Multirate IIR Structures.......................................33
5.1 Mixed Cascade/Parallel Form ...............................................33
5.2 Extra-Ripple IIR Form ...........................................................37
6. Summary ........................................................................................37
3 PRACTICAL MULTIRATE SC CIRCUIT DESIGN CONSIDERATIONS 41
1. Introduction....................................................................................41
2. Power Consumption Analysis ........................................................41
3. Capacitor-Ratio Sensitivity Analysis .............................................44
3.1 FIR Structure ........................................................................44
3.2 IIR Structure ........................................................................46
4. Finite Gain & Bandwidth Effects...................................................49
5. Input-Referred Offset Effects.........................................................49
6. Phase Timing-Mismatch Effects ....................................................55
6.1 Periodic Fixed Timing-Skew Effect........................................55
6.2 Random Timing-Jitter Effects.................................................59
7. Noise Analysis ...............................................................................59
8. Summary ........................................................................................65
4 GAIN- AND OFFSET- COMPENSATION FOR MULTIRATE SC
CIRCUITS 69
1. Introduction....................................................................................69
2. Autozeroing and Correlated-Double Sampling Techniques ..........70
3. AZ and CDS SC Delay Blocks with Mismatch-Free Property ......72
3.1 SC Delay Block Architectures ................................................72
3.2 Gain and Offset Errors – Expressions and Simulation
Verification .....................................................................77
3.3 Multi-Unit Delay Implementations.........................................80
4. AZ and CDS SC Accumulators......................................................82
4.1 SC Accumulator Architectures ...............................................82
4.2 Gain and Offset Errors – Expressions and Simulation
Verificatio n ........................................................................82
5. Design Examples............................................................................84
6. Speed and Power Considerations ...................................................89
7. Summary ........................................................................................94
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Design of Very High-Frequency Multirate Switched-Capacitor Circuits –
Extending the Boundaries of CMOS Analog Front-End Filtering
ix
5 DESIGN OF A 108MHZMULTISTAGE SC VIDEO INTERPOLATING
FILTER 99
1. Introduction....................................................................................99
2. Optimum Architecture Design .....................................................101
2.1 Multistage Polyphase Structure with Half-Band Filtering ..101
2.2 Spread-Reduction Scheme....................................................102
2.3 Coefficient-Sharing Techniques ...........................................103
3. Circuit Design ..............................................................................106
3.1 1st-Stage ...................................................................106
3.2 2nd- and 3rd-Stage .................................................................109
3.3 Digital Clock Phase Generation ..........................................111
4. Circuit Layout ..............................................................................113
5. Simulation Results .......................................................................114
5.1 Behavioral Simulations ........................................................114
5.2 Circuit-Level Simulations.....................................................115
6. Summary ......................................................................................118
6 DESIGN OF A 320MHZ FREQUENCY-TRANSLATED SC BANDPASS
INTERPOLATING FILTER 123
1. Introduction..................................................................................123
2. Prototype System-Level Design...................................................125
2.1 Multi-notch FIR Transfer Function......................................125
2.2 Time-Interleaved Serial ADB Polyphase Structure with
Autozeroing ...................................................................127
3. Prototype Circuit-Level Design ...................................................128
3.1 Autozeroing ADB and Accumulator.....................................128
3.2 High-Speed Multiplexer .......................................................130
3.3 Overall SC Circuit Architecture...........................................133
3.4 Telescopic opamp with Wide-Swing Biasing........................133
3.5 nMOS Switches 136
3.6 Noise Calculation.................................................................137
3.7 I/O Circuitry ...................................................................138
3.8 Low Timing-Skew Clock Generation....................................138
4. Layout Considerations .................................................................143
4.1 Device and Path Matching...................................................143
4.2 Substrate and Supply Noise Decoupling ..............................147
4.3 Shielding ...................................................................151
4.4 Floor Plan ...................................................................151
5. Simulation Results .......................................................................152
5.1 Opamp Simulations ..............................................................152
5.2 Filter Behavioral Simulations ..............................................155
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x Design of Very High-Frequency Multirate Switched-Capacitor Circuits –
Extending the Boundaries of CMOS Analog Front-End Filtering
5.3 Filter Transistor-Level and Post-Layout Simulations.............156
6. Summary ......................................................................................158
7 EXPERIMENTAL RESULTS 163
1. Introduction..................................................................................163
2. PCB Design..................................................................................163
2.1 Floor Plan ...................................................................164
2.2 Power Supplies and Decoupling ..........................................167
2.3 Biasing Currents ..................................................................167
2.4 Input and Output Network....................................................167
3. Measurement Setup and Results ..................................................169
3.1 Frequency Response.............................................................170
3.2 Time-Domain Signal Waveforms .........................................172
3.3 One-Tone Signal Spectrum...................................................172
3.4 Two-Tone Intermodulation Distortion .................................174
3.5 THD and IM3 vs. Input Signal Level....................................177
3.6 Noise Performance...............................................................177
3.7 CMRR and PSRR..................................................................180
4. Summary ......................................................................................181
8 CONCLUSIONS 187
APPENDIX 1 TIMING-MISMATCH ERRORS WITH
NONUNIFORMLY HOLDING EFFECTS....................191
1. Spectrum Expressions for IU-ON(SH) and IN-CON(SH)...........193
1.1 IU-ON(SH) ...................................................................193
1.2 IN-CON(SH) ...................................................................197
2. Closed Form SINAD Expression for IU-ON(SH) and INCON(
SH) .....................................................................................197
2.1 IU-ON(SH) ...................................................................198
2.2 IN-CON(SH) ...................................................................201
3. Closed Form SFDR Expression for IN-CON(SH) systems .........203
4. Spectrum Correlation of IN-OU(IS) and IU-ON(SH)..................205
APPENDIX 2 NOISE ANALYSIS FOR SC ADB DELAY LINE
AND POLYPHASE SUBFILTERS .................................215
1. Output Noise of ADB Delay Line................................................215
2. Output Noise of Polyphase Subfilters ..........................................217
2.1 Using TSI Input Coefficient SC Branches ............................217
2.2 Using OFR Input Coefficient SC Branches..........................220
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Design of Very High-Frequency Multirate Switched-Capacitor Circuits –
Extending the Boundaries of CMOS Analog Front-End Filtering
xi
APPENDIX 3 GAIN, PHASE AND OFFSET ERRORS FOR GOC
MF SC DELAY CIRCUIT I AND J ................................221
1. GOC MF SC Delay Circuit I........................................................221
2. GOC MF SC Delay Circuit J........................................................225

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fanjx

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