Effect of MOSFET Threshold Voltage Variation on High-Performance Circuits

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Effect of MOSFET Threshold Voltage Variation on High-Performance Circuits by Siva G. Narendra Bachelor of Engineering in Electronics and Communication Engineering Government College of Technology, Coimbatore, India, June 1992. Master of Science in Computer Engineering Syracuse University, Syracuse, NY, June 1994. Submitted to the Department of Electrical Engineering and Computer Science in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy in Electrical Engineering and Computer Science at the Massachusetts Institute of Technology January 2002 © 2002 Siva G. Narendra. All rights reserved. The author hereby grants to MIT permission to reproduce and to distribute publicly paper and electronic copies of this thesis document in whole or in part. Signature of Author _______________________________________________________________ Department of Electrical Engineering and Computer Science January 31, 2002 Certified by______________________________________________________________________ Anantha Chandrakasan, Ph.D. Associate Professor of Electrical Engineering Thesis Supervisor Certified by______________________________________________________________________ Dimitri Antoniadis, Ph.D. Professor of Electrical Engineering Thesis Supervisor Accepted by _____________________________________________________________________ Arthur Smith, Ph.D. Professor of Electrical Engineering Graduate Officer

Abstract
The driving force for the semiconductor industry growth has been the elegant scaling nature of
CMOS technology. In future CMOS technology generations, supply and threshold voltages will
have to continually scale to sustain performance increase, limit energy consumption, control power
dissipation, and maintain reliability. These continual scaling requirements on supply and threshold
voltages pose several technology and circuit design challenges. One such challenge is the expected
increase in threshold voltage variation due to worsening short channel effect. This thesis will
address three specific circuit design challenges arising from increased threshold voltage variation
and present prospective solutions. First, with supply voltage scaling, control of die-to-die threshold
voltage variation becomes critical for maintaining high yield. An analytical model will be
developed for existing circuit technique that adaptively biases the body terminal of MOSFET
devices to control this threshold voltage variation. Based on this model, recommendations on how
to effectively use the technique in future technologies will be presented. Second, with threshold
voltage scaling, sub-threshold leakage power is expected to be a significant portion of total power
in future CMOS systems. Therefore, it becomes imperative to accurately predict and minimize
leakage power of such systems, especially with increasing within-die threshold voltage variation.
A model that predicts system leakage based on first principles will be presented and a circuit
technique to reduce system leakage without reducing system performance will be discussed.
Finally, due to different processing steps and short channel effects, threshold voltage of devices of
same or different polarities in the same neighborhood may not be matched. This will introduce
mismatch in the device drive currents that will not be acceptable in some high performance
circuits. In the last part of the thesis, voltage and current biasing schemes that minimize the impact
of neighborhood threshold voltage mismatch will be introduced.

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