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hzfeiyun

Layout for Mixed Analog Digital ICs


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Introduction
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Floor plan strategy
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Cell layout rules
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Layout for reliability
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Layout for min X-talk
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Layout for matching
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Conclusions





[size=117%]•[size=117%]Most of mixed analog/digital chip fails due to the lack of [size=117%]good layout expertise
[size=83%]–[size=83%]matching = f (dimensions, layout)
[size=83%]–[size=83%]cross talk in A/D and D/A
[size=83%]–[size=83%]maximal operation speed limited by wire delay
[size=83%]–[size=83%]reliability (ESD, Latch up)
[size=83%]–[size=83%]EMC/EMI radiation
[size=117%]•[size=117%]A good layout strategy and design is a key to minimal chip [size=117%]area,
minimal layout time and the best performance



[size=133%]•[size=133%]I/O pin placement
–AVDD/AVSS,
DVDD/DVSS
–AGND/REF

–Analog In/Out

–Digital In/Out (Minimal crosstalk to Ain/Aout)
–Test pins
–Xtal In/Out (Close to VDD/VSS)
–Bonding rules





[size=133%]•[size=133%]VDD/VSS Routing
–Min IR drop (metal wide and length,
vias)
–Min ground bounce and on-chip decoupling
–Separate AVDD/AVSS and DVDD/DVSS
–Structured VDD/VSS routing i.s.o noodle type
–Electromigration rules (metal W and contacts)
–ESD/Latchup needs separate wide VDD/VSS lines
–EMC/EMI issue through VDD/VSS (loop area)


[size=133%]•[size=133%]Differential mode radiation
–dt/dt => B(t) loop antenna:
[size=83%]•[size=83%]B(t) [size=83%]µ[size=83%]
I(f) * f[size=54%]2 [size=83%]* A / r

[size=133%]•[size=133%]Common mode radiation
–dv/dt => E(t): wire antenna:
[size=83%]•[size=83%]E(t) [size=83%]µ[size=83%]
I(f) * l * f / r





[size=133%]•[size=133%]Clock Routing
–Clock generator (e.g; XTAL) close to AVDD/AVSS
–Clock for ASP
[size=83%]•[size=83%]VDD/VSS must be Analog supply
[size=83%]•[size=83%]stable level (without ringing)

[size=83%]•[size=83%]low jitter (phase noise)
–Clock for DSP
[size=83%]•[size=83%]driving capability

[size=83%]•[size=83%]min clock skew versus
EMC radiation
[size=83%]•[size=83%]de-phasing with the analog clock for min X-talk




[size=133%]•[size=133%]Cell placement and signal routing
–Data path structure
–Analog cells v.s. digital cells placement
–AGND/VREF must be wide and far from digital
–No digital above and near high Z nodes
–Sensitive node wire must be short

–Critical path (min parasitic RC delay)
–Test pads for critical and important nodes


[size=133%]•[size=133%]Basic rules for cell layout
–Cell area estimation (W/L, R, C, Routing)
–Power supply, In/Out location
–Matching requirement (MOST, R, C)
–Substrate/well contacts (Latch up)
–Do not use Pythagoras rule for spacing
–Layout name = Schematic name (data base structure)
[size=83%]•[size=83%]Use unified cell name for all views (hierarchical and reuse)
[size=83%]–[size=83%]Schematic, layout, symbol, functional, description




[size=133%]•[size=133%]ESD layout rules
–I/O structures for ESD (HBM, CDM model)
–Power supplies protection
–Multiple power supplies protection
–Separate VDD/VSS Ring connecting to bond pads
–Do not use min L devices in the input&output
–A small resistor at output (nMOS)
–Use only approved I/O cells by expert
–



[size=133%]•[size=133%]Latchup layout rule
–Double guard rings in all I/O structures
[size=83%]•[size=83%]to absorb substrate current
–Substrate/Well contacts rules
[size=83%]•[size=83%]to reduce substrate/well resistance
–Distance p+ to nWell
–Low resistive substrate (Epi-wafer)
–





[size=133%]•[size=133%]X-talk noise sources
–Digital switching noise:
[size=83%]•[size=83%]dv/dt =>capacitive/conductive coupling
[size=83%]•[size=83%]di/dt => inductive/conductive coupling
–Analog power output:
[size=83%]•[size=83%]larger di/dt => inductive/conductive coupling
–Parasitic poly gate and substrate resistor noise
[size=83%]•[size=83%]ultra low noise amplifiers
–





[size=133%]•[size=133%]Substrate X-talk (conductive coupling)
–L*di/dt at DVSS => ground bounce
–Kelvin VSS for substrate contact(Latch up???)
–On-chip decoupling techniques
–Multi DVDD/DVSS bonding
–Local substrate shielding
–Fully differential and matched layout
–Slew controlled logic design




[size=133%]•[size=133%]Error in CMOS process
–Absolute error:

DR/R, DC/C,
DVt/Vt,
Db/b > +-20%
–Matching error:
< 0.1% is possible by good circuit design and layout design
[size=133%]&#8226;[size=133%]Matching => Analog accuracy
–Amplifier Gain (R1/R2)
–SC filter time constant (C1/C2)
–Ratio based A/D and D/A accuracy
–Tuning of CT filters (Mosfet-C, Gm-C, Gm-OTA-C)


[size=133%]&#8226;[size=133%]Layout design for matching
–Capacitor matching rules
[size=83%]&#8226;[size=83%]design to limit the capacitor ratio value
[size=83%]&#8226;[size=83%]choice of the unit capacitor area with identical layout structure
[size=83%]&#8226;[size=83%]interdigitate layout,
common centroid structure
[size=83%]&#8226;[size=83%]dummy capacitors for uniform environment
–Resistor matching rules
[size=83%]&#8226;[size=83%]never use small width W resistor
[size=83%]&#8226;[size=83%]choice of the unit resistor value with L ~ 50---100 um
[size=83%]&#8226;[size=83%]identical layout structure &contacts and the same direction
[size=83%]&#8226;[size=83%]dummy resistors for uniform environment


[size=133%]&#8226;[size=133%]Layout design for matching (Contd)
–MOSFET matching rules
[size=83%]&#8226;[size=83%]never use min dimensions (W,L)
[size=83%]&#8226;[size=83%]use the same L for matched MOSFETs
M1&M2
[size=83%]&#8226;[size=83%]define a UNIT MOS such that M2=n*M1
[size=83%]&#8226;[size=83%]the same layout structure for each unit MOS
[size=83%]&#8226;[size=83%]M1&M2 as close as possible and in the same direction
[size=83%]&#8226;[size=83%]cross coupled/common centroid MOS pair


[size=117%]&#8226;[size=117%]For a given design in a given technology,
the layout [size=117%]determines the final chip performance
[size=83%]–[size=83%]floor plan, noise, matching, cross talk, reliability, EMC etc
[size=117%]&#8226;[size=117%]Good layout strategy leads to minimal chip area,
minimal [size=117%]layout time and the best performance
[size=117%]&#8226;[size=117%]Expertise in layout design is a basis for a good IC designer

nesta

是什么啊？

bennykc2

water

semico_ljj

semico_ljj

Layout for Mixed Analog Digital ICs t Introduction t Floor plan strategy t Cell layout rules t Layout for reliability t Layout for min X-talk t Layout for matching t Conclusions &#8226;Most of mixed analog/digital chip fails due to the lack of good layout expertise –matching = f (dimensions, layout) –cross talk in A/D and D/A –maximal operation speed limited by wire delay –reliability (ESD, Latch up) –EMC/EMI radiation &#8226;A good layout strategy and design is a key to minimal chip area, minimal layout time and the best performance &#8226;I/O pin placement –AVDD/AVSS, DVDD/DVSS –AGND/REF –Analog In/Out –Digital In/Out (Minimal crosstalk to Ain/Aout) –Test pins –Xtal In/Out (Close to VDD/VSS) –Bonding rules &#8226;VDD/VSS Routing –Min IR drop (metal wide and length, vias) –Min ground bounce and on-chip decoupling –Separate AVDD/AVSS and DVDD/DVSS –Structured VDD/VSS routing i.s.o noodle type –Electromigration rules (metal W and contacts) –ESD/Latchup needs separate wide VDD/VSS lines –EMC/EMI issue through VDD/VSS (loop area) &#8226;Differential mode radiation –dt/dt => B(t) loop antenna: &#8226;B(t) &micro; I(f) * f2 * A / r &#8226;Common mode radiation –dv/dt => E(t): wire antenna: &#8226;E(t) &micro; I(f) * l * f / r &#8226;Clock Routing –Clock generator (e.g; XTAL) close to AVDD/AVSS –Clock for ASP &#8226;VDD/VSS must be Analog supply &#8226;stable level (without ringing) &#8226;low jitter (phase noise) –Clock for DSP &#8226;driving capability &#8226;min clock skew versus EMC radiation &#8226;de-phasing with the analog clock for min X-talk &#8226;Cell placement and signal routing –Data path structure –Analog cells v.s. digital cells placement –AGND/VREF must be wide and far from digital –No digital above and near high Z nodes –Sensitive node wire must be short –Critical path (min parasitic RC delay) –Test pads for critical and important nodes &#8226;Basic rules for cell layout –Cell area estimation (W/L, R, C, Routing) –Power supply, In/Out location –Matching requirement (MOST, R, C) –Substrate/well contacts (Latch up) –Do not use Pythagoras rule for spacing –Layout name = Schematic name (data base structure) &#8226;Use unified cell name for all views (hierarchical and reuse) –Schematic, layout, symbol, functional, description &#8226;ESD layout rules –I/O structures for ESD (HBM, CDM model) –Power supplies protection –Multiple power supplies protection –Separate VDD/VSS Ring connecting to bond pads –Do not use min L devices in the input&output –A small resistor at output (nMOS) –Use only approved I/O cells by expert – &#8226;Latchup layout rule –Double guard rings in all I/O structures &#8226;to absorb substrate current –Substrate/Well contacts rules &#8226;to reduce substrate/well resistance –Distance p+ to nWell –Low resistive substrate (Epi-wafer) – &#8226;X-talk noise sources –Digital switching noise: &#8226;dv/dt =>capacitive/conductive coupling &#8226;di/dt => inductive/conductive coupling –Analog power output: &#8226;larger di/dt => inductive/conductive coupling –Parasitic poly gate and substrate resistor noise &#8226;ultra low noise amplifiers – &#8226;Substrate X-talk (conductive coupling) –L*di/dt at DVSS => ground bounce –Kelvin VSS for substrate contact(Latch up???) –On-chip decoupling techniques –Multi DVDD/DVSS bonding –Local substrate shielding –Fully differential and matched layout –Slew controlled logic design &#8226;Error in CMOS process –Absolute error: DR/R, DC/C, DVt/Vt, Db/b > +-20% –Matching error: < 0.1% is possible by good circuit design and layout design &#8226;Matching => Analog accuracy –Amplifier Gain (R1/R2) –SC filter time constant (C1/C2) –Ratio based A/D and D/A accuracy –Tuning of CT filters (Mosfet-C, Gm-C, Gm-OTA-C) &#8226;Layout design for matching –Capacitor matching rules &#8226;design to limit the capacitor ratio value &#8226;choice of the unit capacitor area with identical layout structure &#8226;interdigitate layout, common centroid structure &#8226;dummy capacitors for uniform environment –Resistor matching rules &#8226;never use small width W resistor &#8226;choice of the unit resistor value with L ~ 50---100 um &#8226;identical layout structure &contacts and the same direction &#8226;dummy resistors for uniform environment &#8226;Layout design for matching (Contd) –MOSFET matching rules &#8226;never use min dimensions (W,L) &#8226;use the same L for matched MOSFETs M1&M2 &#8226;define a UNIT MOS such that M2=n*M1 &#8226;the same layout structure for each unit MOS &#8226;M1&M2 as close as possible and in the same direction &#8226;cross coupled/common centroid MOS pair &#8226;For a given design in a given technology, the layout determines the final chip performance –floor plan, noise, matching, cross talk, reliability, EMC etc &#8226;Good layout strategy leads to minimal chip area, minimal layout time and the best performance &#8226;Expertise in layout design is a basis for a good IC designer

lurx0025

thank you

semico_ljj

以上就是内容！content

hgdllt

免费看Layout for Mixed Analog Digital ICs

freebirdlee

牛,还要回复.